Semiconductor memory device having back-bias voltage in...

Details Semiconductor memory device having back-bias voltage in... Semiconductor memory device having back-bias voltage in...

2011-04-12

2011-04-12

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S536000

Reexamination Certificate

active

07924073

ABSTRACT:
A back-bias voltage generating circuit controls the back-bias voltage in a predetermined range by detecting the back-bias voltage in case the back-bias voltage level decreases below a predetermined target level. The circuit includes first and second detecting units outputting respective detection signals, which detect a voltage level of the terminal based on respective higher first and lower second target levels. An oscillator generates an oscillation signal that oscillates at a predetermined frequency, in response to a detection signal of the first voltage detecting unit. A charge pumping unit drives the terminal by performing charge pumping in response to the oscillation signal. A voltage level control unit controls the voltage level of the terminal in response to the detection signals, whereby the terminal's voltage level is lower than the first target level and higher than the second target level.

REFERENCES:
patent: 6016072 (2000-01-01), Ternullo et al.
patent: 7397282 (2008-07-01), Mizuno et al.
patent: 2008/0150505 (2008-06-01), Abe
patent: 1020040006730 (2004-01-01), None
patent: 1020040051743 (2004-06-01), None
patent: 1020070030557 (2007-03-01), None
patent: 1020070101911 (2007-10-01), None
Notice of Prelimary Rejection issued from Korean Intellectual Property Office on Apr. 28, 2009 with an English Translation.
Notice of Allowance issued from Korean Intellectual Property Office on Aug. 7, 2009 with an English Translation.

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