Static information storage and retrieval – Powering
Reexamination Certificate
2001-07-31
2004-05-11
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Powering
C365S227000, C365S228000, C365S229000, C365S149000, C365S154000
Reexamination Certificate
active
06735141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having an SRAM (static random access memory) and a DRAM (dynamic random access memory) that are provided on a single chip.
2. Description of the Related Art
For example, in conventional portable telephones, SRAMs were often employed as the memory device. Recently, however, there is a demand for portable telephones that are equipped with large-capacity memory devices, such as DRAMs, in order to promote the interfacing between the portable telephones and the Internet.
Generally, in a DRAM memory cell, a read operation must be followed by a subsequent write operation. Charge stored on the capacitor of the memory cell does not remain on the capacitor indefinitely. Due to a variety of leakage paths, the charge can eventually leak off the capacitor, causing the memory cell to loose its information. To alleviate this problem, each memory cell in the DRAM must be periodically read, sensed, and re-written to a full level. This refresh requirement distinguishes the DRAM from the SRAM.
If a portable telephone is equipped with the DRAM, instead of the SRAM, the power consumption in its standby state will be increased since the DRAM requires periodical refresh operations to retain the stored information. Although the recent demand for large-capacity memory devices is met by the DRAM-equipped portable telephone, the time that allows the portable telephone to continuously work in the standby state will be considerably reduced.
The SRAM does not require the refresh operations to retain the stored information and hardly consumes the power during its standby state. However, the density of the storage elements in the SRAM is low compared to the density of the storage elements in the DRAM. If a portable telephone is equipped with a large quantity of the SRAM devices that meets the memory capacity needed by the recent demand, the cost will be significantly increased.
SUMMARY OF THE INVENTION
In order to overcome the problems described above, preferred embodiments of the present invention provide an improved semiconductor memory device that reduces the power consumption of the entire system to a level lower than the power consumption level of the DRAM-only system and avoids the increase of the cost of the SRAM-only system while meeting the large memory capacity needed.
According to one preferred embodiment of the present invention, a semiconductor memory device includes: an SRAM which is provided on a chip, the SRAM including an SRAM cell array; a DRAM which is provided on the chip, the DRAM including a DRAM cell array; and an address signal which has a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
The semiconductor memory device of the preferred embodiment includes the SRAM and the DRAM provided on a single chip. The semiconductor memory device of the present invention is effective in reducing the power consumption of the entire system to a level lower than the power consumption level of the DRAM-only system and in avoiding the increase of the cost of the SRAM-only system while meeting the large memory capacity needed.
In another preferred embodiment of the semiconductor device of the invention, a semiconductor memory device includes: an SRAM memory block which is provided on a chip, the SRAM memory block including an SRAM cell array; a DRAM memory block which is provided on the chip, the DRAM memory block including a DRAM cell array; and a source voltage which is externally supplied to the DRAM memory block when the DRAM cell array is accessed, the source voltage to the DRAM memory block being set to a ground voltage when the DRAM cell array is not accessed.
The semiconductor memory device of the above preferred embodiment of the invention is effective in reducing the power consumption when the DRAM is not used. Further, the semiconductor memory device of the present invention is effective in reducing the power consumption of the entire system to a level lower than the power consumption level of the DRAM-only system and in avoiding the increase of the cost of the SRAM-only system while meeting the large memory capacity needed.
In another preferred embodiment of the semiconductor device of the invention, a semiconductor memory device includes: an SRAM memory block which is provided on a chip, the SRAM memory block including an SRAM cell array; a DRAM memory block which is provided on the chip, the DRAM memory block including a DRAM cell array and an internal power supply circuit, the internal power supply circuit producing control voltages that are internally supplied to the DRAM memory block; and a control unit which controls the internal power supply circuit based on control signals that are externally supplied to the control unit, wherein, when the DRAM cell array is not accessed, the control unit controls the internal power supply circuit based on the control signals so that an operation of the internal power supply circuit is stopped and the control voltages are set in a predetermined condition.
The semiconductor device of the above preferred embodiment of the invention is effective in reducing the power consumption of the entire system to a level lower than the power consumption level of the DRAM-only system and in avoiding the increase of the cost of the SRAM-only system while meeting the large memory capacity needed.
In another preferred embodiment of the semiconductor device of the invention, a semiconductor memory device includes: an SRAM memory block which is provided on a chip, the SRAM memory block including an SRAM cell array; a DRAM memory block which is provided on the chip, the DRAM memory block having a DRAM cell array; and a control unit which is connected to each of the SRAM memory block and the DRAM memory block, the control unit including a first pad and a second pad, the control unit activating an operation of one of the SRAM memory block or the DRAM memory block based on a combination of a first control value indicated by a first control signal presented to the first pad and a second control value indicated by a second control signal presented to the second pad.
The semiconductor device of the above preferred embodiment of the invention is effective in reducing the power consumption of the entire system to a level lower than the power consumption level of the DRAM-only system and in avoiding the increase of the cost of the SRAM-only system while meeting the large memory capacity needed.
In another preferred embodiment of the semiconductor device of the invention, a semiconductor memory device includes: an SRAM memory block which is provided on a chip, the SRAM memory block including an SRAM cell array having bit lines connected to column switches, the column switches connected to a data bus; a DRAM memory block which is provided on the chip, the DRAM memory block including a DRAM cell array, sense amplifiers and column gates, the DRAM cell array having bit lines connected to the column gates, the column gates connected to the data bus; and column select signals which are provided to the column gates in order to select which sense amplifier output to connect to the data bus, wherein, when accessing the SRAM cell array during a refresh operation of the DRAM cell array, all the column select signals are set to OFF state so that all the column gates are turned off by the column select signals.
The semiconductor device of the above preferred embodiment of the invention is effective in reducing the power consumption of the entire system to a level lower than the power consumption level of the DRAM-only system and in avoiding the increase of the cost of the SRAM-only system while meeting the large memory capacity needed.
REFERENCES:
patent: 5471421 (1995-11-01), Rose et al.
patent: 5606265 (19
Fujioka Shin-ya
Funyu Akihiro
Ikeda Hitoshi
Sato Kotoku
Satoh Kimiaki
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
Yoha Connie C.
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