Semiconductor memory device having an improved wiring and decode

Details Semiconductor memory device having an improved wiring and decode Semiconductor memory device having an improved wiring and decode

1997-12-31

2000-08-08

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

36523003, 36523006, G11C 700

Patent

active

RE036813&

ABSTRACT:
Word lines of a memory cell array are coupled to the output portion of a first decoder while the input portion of the first decoder is coupled to a plurality of signal lines which are elongated on the memory cell array. The signal lines are provided for a predetermined plurality of word lines, and each of said signal lines can be coupled to the word lines by switching devices. Preferably, the signal lines can be formed of a low resistance material such as aluminum to enhance the speed while the word lines can be formed of polycrystalline silicon to allow simultaneous formation with the memory cell gate electrodes. By virtue of providing each signal line for more than one word line, the design requirements for the signal lines are less stringent than previous arrangements wherein a one-to-one relationship has been attempted between polycrystalline silicon word lines and aluminum connection lines. A further feature of the present invention is the use of a second decoder having an output portion coupled to the signal lines and an input portion coupled to receive selection signals for selecting a predetermined one of the signal lines.

REFERENCES:
patent: 3560940 (1971-02-01), Gaensslen
patent: 4618945 (1986-10-01), Sakurai et al.

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