Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-05-30
2006-05-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S230080
Reexamination Certificate
active
07054225
ABSTRACT:
A semiconductor memory device includes of a plurality of sense amplifiers. The sense amplifiers are arranged in two amplifier columns. The two amplifier columns are disposed between two cell columns of cell plates. An address circuitry, an ATD circuitry, and a delay circuitry are disposed between an input pin row and the two cell columns. An ATD pulse synthesizer is disposed between the two amplifier columns and spaced a predetermined signal transmission path from the ATD and delay circuitries.
REFERENCES:
patent: 6337810 (2002-01-01), Yamasaki et al.
patent: 6625706 (2003-09-01), Campanale et al.
Elms Richard
NEC Electronics Corporation
Nguyen Hien
Scully , Scott, Murphy & Presser, P.C.
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