Semiconductor memory device having address transition detection

Details Semiconductor memory device having address transition detection Semiconductor memory device having address transition detection

1997-02-26

1998-05-26

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365233, G11C 700

Patent

active

057577188

ABSTRACT:
In a semiconductor memory device including: an address buffer for generating an address signal, a memory cell array for generating a first data signal in response to the address signal, a sense amplifier circuit for sensing the first data signal to generate a second data signal in response to a sense activation signal, a data latch circuit for latching the second data signal to generate a third data signal in response to a latch activation signal, an address transition detection circuit for detecting a transition of the address signal to generate an address transition detection signal, and a timing generating unit for generating the sense activation signal and the latch activation signal, the timing generating unit is formed by a plurality of timing generating circuits for prolonging the address transition detection signal by different delay times to generate pulse width signals. The delay times have different characteristics depending upon a power supply voltage. Also, a logic circuit logically adds the pulse width signals to each other to generate a logic signal. A pulse prolonging circuit prolongs the logic signal by a definite time to generate the sense activation signal, and a pulse generating circuit generates the logic signal in response to a termination of the logic signal.

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