Semiconductor memory device having a time variable sense amplifi

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365205, 365207, 365194, G11C 700

Patent

active

053863895

ABSTRACT:
A semiconductor memory is set in a required operation mode according to an external instruction. The memory properly controls the activation timing of a sense amplifier (1) incorporated in the memory. The memory is capable of surely amplifying a voltage difference between bit lines in every operation mode with no delay in access time, to achieve a high-speed operation.
The memory has the sense amplifier (1) for detecting and amplifying a voltage difference between complementary bit lines that transfer data to and from a corresponding memory cell, and a unit (2) for changing the activation timing of the sense amplifier according to an externally instructed operation mode (C).

REFERENCES:
patent: 4716551 (1987-12-01), Inagaki
patent: 4811290 (1989-03-01), Watanabe
patent: 5007024 (1991-04-01), Tanaka et al.

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