Semiconductor memory device having a synchronous DRAM

Static information storage and retrieval – Addressing – Counting

Patent

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Details

365191, 365222, 36523006, G11C 800

Patent

active

060381965

ABSTRACT:
This invention relates to a semiconductor memory device and uses a row address counter as well as an internal column address counter for a burst write and read. One address counter which is a combination of a refresh address counter and a burst column address counter is provided to decrease chip area and simulation time of operation waveform.

REFERENCES:
patent: 5446696 (1995-08-01), Ware et al.
patent: 5659515 (1997-08-01), Matsuo et al.
patent: 5812488 (1998-09-01), Zagar et al.
patent: 5867438 (1999-02-01), Nomura et al.

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