Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2003-01-10
2004-06-01
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Powering
Data preservation
C365S226000, C365S194000, C365S189090, C365S189110, C365S233100, C365S230060, C327S535000, C327S537000, C327S538000
Reexamination Certificate
active
06744689
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a power supply circuit generating an internal power supply voltage of a stable voltage level built therein.
2. Description of the Background Art
As a semiconductor memory device of large capacity inputting/outputting data at high speed, a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has come into practical use.
The DDR-SDRAM inputs/outputs data in synchronization with rising and falling of a periodic signal. To this end, the DDR-SDRAM has a DLL (Delay Locked Loop) circuit generating the periodic signal built therein.
The DDR-SDRAM externally receives complementary clocks CLK, /CLK having a phase difference of 180° with each other. The DLL circuit receives buffered clocks CLK, /CLK, i.e., clocks BUFF_CLK, BUFF_/CLK, and uses the received clocks BUFF_CLK, BUFF_/CLK to generate periodic signals DLLCLK_P, DLLCLK_N.
Generation of periodic signals DLLCLK_P, DLLCLK_N is now described with reference to FIG.
28
. The DDR-SDRAM is provided with a VDC (Voltage Down Converter) circuit
1000
and a DLL circuit
1100
.
VDC circuit
1000
down coverts and external power supply voltage EXTVDD supplied from the outside of the DDR-SDRAM to a voltage level of a reference voltage VREFP generated within the DDR-SDRAM, to generate an internal power supply voltage VDD4. It provides the generated internal power supply voltage VDD4 to DLL circuit
1100
.
DLL circuit
1100
receives clocks BUFF_CLK, BUFF_/CLK, supplied from the outside of the DDR-SDRAM and having undergone buffering, and internal power supply voltage VDD4, and generates periodic signals DLLCLK_P, DLLCLK_N having phases corresponding to the voltage level of internal power supply voltage VDD4. Periodic signal DLLCLK_P has a phase difference of 180° with respect to periodic signal DLLCLK_N. DLL circuit
1100
, when locked to an external clock EXTCLK, normally generates periodic signal DLLCLK_P constantly at the same timing with respect to the external clock EXTCLK.
In the DDR-SDRAM, data are input/output in synchronization with periodic signals DLLCLK_P, DLLCLK_N.
Here, there is a problem that the voltage level of external power supply voltage EXTVDD changes. When a noise is superimposed on external power supply voltage EXTVDD, there occurs no problem if the voltage level of internal power supply voltage VDD4 is sufficiently lower than the voltage level of external power supply voltage EXTVDD. However, if the voltage level of internal power supply voltage VDD4 is close to that of external power supply voltage EXTVDD, the noise would be transmitted to internal power supply voltage VDD4. As a result, the rising timing of periodic signal DLLCLK_P would become off the rising timing of external clock EXTCLK.
Specifically, as shown in
FIG. 29
, in the region where external power supply voltage EXTVDD is free from noise, periodic signal DLLCLK_P always rises at the same timing with respect to the rising of external clock EXTCLK. However, in the region from timing t1 to timing t2 where a noise is superimposed on external power supply voltage EXTVDD, the noise is also superimposed on internal power supply voltage VDD4, and each rising timing of periodic signal DLLCLK_P comes off the respective rising timing of external clock EXTCLK.
In this case, it is difficult for the DDR-SDRAM to input/output data at constant timings.
Such a phase shift of periodic signal DLLCLK_P due to the change of voltage level of external power supply voltage EXTVDD will be prevented if the voltage level of internal power supply voltage VDD4 is kept sufficiently lower than the voltage level of external power supply voltage EXTVDD. If the voltage level of internal power supply voltage VDD4 is made sufficiently low, however, the delay amount in the DLL circuit will increase, which makes minute control on the order of pico-seconds (ps) difficult, so that the operating margin will decrease. As such, it is difficult to keep internal power supply voltage VDD4 to be provided to the DLL circuit at a sufficiently low level.
Japanese Patent Laying-Open No. 2000-40394 discloses an invention related to a DRAM provided with two different power supply circuits. In the invention, one power supply circuit generates a first power supply voltage, and the other power supply circuit generates a second power supply voltage whose voltage level is higher than that of the first power supply voltage.
When the voltage level of the second power supply voltage decreases, the voltage level of the first power supply voltage is decreased such that the voltage level of the first power supply voltage becomes lower than that of the second power supply voltage.
Assume that the first and second power supply voltages correspond to the internal power supply voltage VDD4 and the external power supply voltage EXTVDD herein, respectively. If the internal power supply voltage VDD4 is decreased in accordance with the decrease of external power supply voltage EXTVDD, the operating margin will decrease as described above, hindering a stable operation of the DDR-SDRAM.
The invention of Japanese Patent Laying-Open No. 2000-40394 controls the voltage level of the first power supply voltage in accordance with the voltage level of the second power supply voltage. It does not intend to stabilize the voltage level of one of the power supply voltages.
SUMMARY OF THE INVENTION
Based on the foregoing, an object of the present invention is to provide a semiconductor memory device having a power supply circuit built therein which generates an internal power supply voltage prevented from suffering an influence of an external power supply voltage and permitting a stable operation of the semiconductor memory device.
According to the present invention, the semiconductor memory device includes: a memory cell array storing data; a power supply circuit changing a voltage level of an external power supply voltage to generate a first internal power supply voltage and changing a voltage level of the generated first internal power supply voltage to generate a second internal power supply voltage; a periodic signal generating circuit generating a periodic signal having a phase corresponding to a voltage level of the second internal power supply voltage provided from the power supply circuit; and an output circuit externally outputting read data read out from the memory cell array, in synchronization with the periodic signal
In the semiconductor memory device of the present invention, the second internal power supply voltage used in the periodic signal generating circuit is generated by changing the voltage level of the external power supply voltage.
As such, according to the present invention, an internal power supply voltage having a stable voltage level and unlikely to suffer an influence of noise superimposed on the external power supply voltage can be generated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6385119 (2002-05-01), Kobayashi et al.
patent: 6496438 (2002-12-01), Saito
patent: 6498760 (2002-12-01), Yamasaki
patent: 6661729 (2003-12-01), Yamasaki
patent: P2000-40394 (2000-02-01), None
McDermott & Will & Emery
Renesas Technology Corp.
Tran Andrew Q.
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