Semiconductor memory device having a sleep mode

Static information storage and retrieval – Powering – Conservation of power

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365229, C11C 700

Patent

active

055638392

ABSTRACT:
The present invention provides a computer memory device having a sleep mode characterized by extremely low current consumption and relatively large turn on delay. The invention includes circuitry for disabling current sinking elements internal to said device in response to a sleep signal. In one embodiment, the invention includes circuitry for disconnecting the bit lines and memory cell loads of a nonvolatile static random access memory (nvSRAM) array from a source of power in response to a sleep signal. This embodiment is capable of first transferring the data stored in a volatile portion of the array to a nonvolatile portion of the array before entering sleep mode to prevent loss of the data.

REFERENCES:
patent: 4758945 (1988-07-01), Remedi
patent: 4984211 (1991-01-01), Tran
patent: 5121359 (1992-06-01), Steele
patent: 5262998 (1993-11-01), Mnich et al.
patent: 5345424 (1994-06-01), Landgraf
Simtek Data Book, Mar. 7, 1994, pp. 1-14.

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