Semiconductor memory device having a relaxed pitch for sense...

Details Semiconductor memory device having a relaxed pitch for sense... Semiconductor memory device having a relaxed pitch for sense...

1996-07-29

2003-01-28

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S201000

Reexamination Certificate

active

06512717

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device having a relaxed sense amplifier arrangement.
In semiconductor memory devices and integrated circuits, a typical example being a dynamic random access memory (DRAM), bit line pairs are disposed with ever decreasing mutual separation or pitch with the increase in the integration density. In relation to such a decrease in the pitch of the bit line pairs, there emerges a difficulty for laying out sense amplifiers with a pitch identical to the pitch of the bit line pairs.
In order to overcome the problem and to achieve a further increase of integration density, a so-called relaxed sense amplifier arrangement is proposed for the array of sense amplifiers.
FIG. 1
shows the overall construction of a DRAM that uses a relaxed sense amplifier arrangement.
Referring to
FIG. 1
, the DRAM includes a core area
1
that in turn includes arrays of memory cells referred to hereinafter as memory blocks, wherein each memory block includes an array of sense amplifiers. A part of the core area
1
is shown in detail in a plan view of FIG.
2
. The memory blocks forming the core area
1
are selected by a block address signal such as block address signals BA
0
and BA
1
.
Hereinafter, the construction of the core area
1
will be explained first with reference to FIG.
2
.
Referring to
FIG. 2
, the core area
1
includes memory blocks A
0
and A
1
, B
0
and B
1
, C
0
and C
1
, D
0
and D
1
each formed of a memory cell array, wherein the memory blocks A
0
and A
1
form together a memory block having a block address [
00
], the memory blocks B
0
and B
1
form together a memory block having a block address [
01
], the memory blocks C
0
and C
1
form together a memory block having a block address [
01
], and the memory blocks D
0
and D
1
form together a memory block having a block address [
11
].
Further, there is provided a sense amplifier array S
00
in the core area
1
, wherein the sense amplifier array S
00
includes sense amplifiers corresponding to odd number bit line pairs extending in the memory block A
0
such as the one formed of bit lines BL-A
00
and /BL-A
00
.
Similarly, there is provided a sense amplifier array S
01
including sense amplifiers that correspond to even number bit line pairs in the memory blocks A
0
and B
0
, such as the bit line pair formed of bit lines BL-A
01
and /BL-A
01
or the bit line pair formed of bit lines BL-B
01
and /BL-B
01
.
Further, there is provided a sense amplifier array S
10
including sense amplifiers that correspond to odd number bit line pairs in the memory blocks B
0
and C
0
, such as the bit line pair formed of bit lines BL-B
00
and /BL-B
00
or the bit line pair formed of bit lines BL-C
00
and /BL-C
00
.
Further, there is provided a sense amplifier array S
11
including sense amplifiers that correspond to even number bit line pairs in the memory blocks C
0
and D
0
, such as the bit line pair formed of bit lines BL-C
01
and /BL-C
01
or the bit line pair formed of bit lines BL-D
01
and /BL-D
01
.
Further, there is provided a sense amplifier array S
20
including sense amplifiers that correspond to odd number bit line pairs in the memory blocks D
0
and A
1
, such as the bit line pair formed of bit lines BL-D
00
and /BL-D
00
or the bit line pair formed of bit lines BL-A
10
and /BL-A
10
.
Further, there is provided a sense amplifier array S
21
including sense amplifiers that correspond to even number bit line pairs in the memory blocks A
1
and B
1
, such as the bit line pair formed of bit lines BL-A
11
and /BL-A
11
or the bit line pair formed of bit lines BL-B
11
and /BL-B
11
.
Further, there is provided a sense amplifier array S
30
including sense amplifiers that correspond to odd number bit line pairs in the memory blocks B
1
and C
1
, such as the bit line pair formed of bit lines BL-B
10
and /BL-B
10
or the bit line pair formed of bit lines BL-C
10
and /BL-C
10
.
Further, there is provided a sense amplifier array S
31
including sense amplifiers that correspond to even number bit line pairs in the memory blocks C
1
and D
1
, such as the bit line pair formed of bit lines BL-C
11
and /BL-C
11
, or the bit line pair formed of bit lines BL-D
11
and /BL-D
11
.
Further, there is provided a sense amplifier array S
40
including sense amplifiers that correspond to odd number bit line pairs in the memory blocks D
1
, such as the bit line pair formed of bit lines BL-D
10
and /BL-D
10
.
As the sense amplifiers corresponding only to the odd number bit line pairs or only to the even number bit line pairs are thus aligned in each of the sense amplifier arrays S
00
, S
01
, S
10
, S
11
, S
20
, S
21
, S
30
, S
31
and S
40
in such a DRAM having the relaxed sense amplifier arrangement, a sufficient mutual separation is secured between adjacent sense amplifiers in each of the sense amplifier arrays.
Further, the core area
1
includes data lines LDB
00
and /LDB
00
referred to hereinafter as local data bus, wherein the local data bus (LDB
00
, /LDB
00
) corresponds to the sense amplifier array S
00
and is connected commonly to the odd number bit line pairs included in the memory block A
0
such as the bit line pair (BL-A
00
, /BL-A
00
).
Similarly, there is provided a local data bus (LDB
01
, /LDB
01
) in correspondence to the sense amplifier array Sol such that the local data bus (LDB
01
, /LDB
01
) is connected commonly to the even number bit line pairs included in the memory blocks A
0
and B
0
such as the bit line pair (BL-A
01
, /BL-A
01
) or (BL-B
01
, /BL-B
01
).
Further, there is provided a local data bus (LDB
10
, /LDB
10
) in correspondence to the sense amplifier array S
10
such that the local data bus (LDB
10
, /LDB
10
) is connected commonly to the odd number bit line pairs included in the memory blocks B
0
and C
0
such as the bit line pair (BL-B
00
, /BL-B
00
) or (BL-C
00
, /BL-C
00
).
Further, there is provided a local data bus (LDB
11
, /LDB
11
) in correspondence to the sense amplifier array S
11
such that the local data bus (LDB
11
, /LDB
11
) is connected commonly to the even number bit line pairs included in the memory blocks C
0
and D
0
such as the bit line pair (BL-C
01
, /BL-C
01
) or (BL-D
01
, /BL-D
01
).
Further, there is provided a local data bus (LDB
20
, /LDB
20
) in correspondence to the sense amplifier array S
20
such that the local data bus (LDB
20
, /LDB
20
) is connected commonly to the odd number bit line pairs included in the memory blocks D
0
and A
10
such as the bit line pair (BL-D
00
, /BL-D
00
) or (BL-A
10
, /BL-A
10
).
Further, there is provided a local data bus (LDB
21
, /LDB
21
) in correspondence to the sense amplifier array S
21
such that the local data bus (LDB
21
, /LDB
21
) is connected commonly to the even number bit line pairs included in the memory blocks A
1
and B
1
such as the bit line pair (BL-A
11
, /BL-A
11
) or (BL-B
11
, /BL-B
11
).
Further, there is provided a local data bus (LDB
30
, /LDB
30
) in correspondence to the sense amplifier array S
30
such that the local data bus (LDB
30
, /LDB
30
) is connected commonly to the odd number bit line pairs included in the memory blocks B
1
and C
1
such as the bit line pair (BL-B
10
, /BL-B
10
) or (BL-C
10
, /BL-C
10
).
Further, there is provided a local data bus (LDB
31
, /LDB
31
) in correspondence to the sense amplifier array S
31
such that the local data bus (LDB
31
, /LDB
31
) is connected commonly to the even number bit line pairs included in the memory blocks C
1
and D
1
such as the bit line pair (BL-C
11
, /BL-C
11
) or (BL-D
11
, /BL-D
11
).
Further, there is provided a local data bus (LDB
40
, /LDB
40
) in correspondence to the sense amplifier array S
40
such that the local data bus (LDB
40
, /LDB
40
) is connected commonly to the odd number bit line pairs included in the memory block D
1
such as the bit line pair (BL-D
10
, /BL-D
10
).
FIG. 3
shows a part of the memory blocks A
0
and B
0
as well as a part o

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