Semiconductor memory device having a prolonged data holding time

Details Semiconductor memory device having a prolonged data holding time Semiconductor memory device having a prolonged data holding time

1994-01-24

1995-06-20

Popek, Joseph A.

Static information storage and retrieval

Powering

365228, 365229, G11C 514

Patent

active

054266017

ABSTRACT:
An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.

REFERENCES:
patent: 4977537 (1990-12-01), Dias et al.
patent: 5321653 (1994-06-01), Suh et al.
M. Aoki et al., "A 1.5V DRAM for Battery-Based Applications", 1989 IEEE International Solid-State Circuits Conference, pp. 238-240 (Feb. 17, 1989).

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