Semiconductor memory device having a power-down mode

Details Semiconductor memory device having a power-down mode Semiconductor memory device having a power-down mode

1998-08-11

2000-07-11

Mai, Son

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365227, G11C 800

Patent

active

060882905

ABSTRACT:
When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.

REFERENCES:
patent: 5337285 (1994-08-01), Ware et al.
patent: 5623453 (1997-04-01), Shinozaki
patent: 5719812 (1998-02-01), Seki et al.

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