Semiconductor memory device having a plurality of SRAMs operable

Details Semiconductor memory device having a plurality of SRAMs operable Semiconductor memory device having a plurality of SRAMs operable

1991-07-15

1993-11-23

Callahan, Timothy P.

Static information storage and retrieval

Addressing

Sync/clocking

365236, 307480, 328 63, G11C 800, H03K 1900

Patent

active

052650634

ABSTRACT:
A semiconductor memory device having a plurality of (N) SRAMs (Static Random Access Memories). The device equally divides all of the data into N blocks and writes each of the N blocks of data in respective one the N SRAMs. In a read mode operation, the device reads different data from the N SRAMs at the same time. This is successful in reducing the chip area and current consumption.

REFERENCES:
patent: 3855580 (1974-12-01), Lighthall
patent: 4503490 (1985-03-01), Thompson
patent: 4829485 (1989-05-01), Hatanaka et al.
patent: 4852061 (1989-07-01), Baron et al.

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