Semiconductor memory device having a plurality of memory cells o

Details Semiconductor memory device having a plurality of memory cells o Semiconductor memory device having a plurality of memory cells o

1987-10-07

1989-09-12

Hille, Rolf

357 55, 357 41, H01L 2978, H01L 2906, H01L 2702

Patent

active

048664944

ABSTRACT:
A new memory device of single transistor type is disclosed. A substrate has a surface portion of low impurity concentration and an inner portion of high impurity concentration, and a trench is formed in the substrate from the surface portion into the inner portion such that the trench surrounds a cell section of the substrate. A switching transistor is formed in the surface portion at the cell section, and a capacitor is formed in the trench such that a MOS type capacitor is constituted by a capacitor electrode, the lower side wall by the inner portion of the substrate and an insulating film therebetween. A bit line is connected to a conductive layer provided at the upper part of the trench, and the conductive layer is connected to the source or drain region of the transistor.

REFERENCES:
patent: 4672410 (1987-06-01), Miura et al.
"High Density Vertical DRAM Cell", IBM Technical Disclosure Bulletin, vol. 29, No. 5, Oct. 1986, pp. 2335-2340.

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