Semiconductor memory device having a plurality of I/O terminal g

Details Semiconductor memory device having a plurality of I/O terminal g Semiconductor memory device having a plurality of I/O terminal g

1996-02-07

1997-04-22

Nguyen, Tan T.

Boots, shoes, and leggings

36518905, 365233, G11C 700

Patent

active

056234473

ABSTRACT:
There are provided upper and lower data I/O terminal groups, each forming a unit for input/output of data. When an early write detecting circuit included in a clock generating circuit detects designation of an early write mode and one of the groups is designated for writing, lower or upper input buffers controlled by write control circuit takes in the data. Concurrently, in response to the detection of mode, lower or upper output buffer uses, for reading, the other group not taking in data for writing. In this mode, therefore, the write and read operations are executed simultaneously. Thereby, simultaneous operation of the write and read data is allowed, and a data processing speed is improved.

REFERENCES:
patent: 5204841 (1993-04-01), Chappell et al.
patent: 5276842 (1994-01-01), Sugita
patent: 5315560 (1994-05-01), Nishimoto et al.
patent: 5541886 (1996-07-01), Hasbun

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