Semiconductor memory device having a plurality of banks activate

Details Semiconductor memory device having a plurality of banks activate Semiconductor memory device having a plurality of banks activate

1998-11-24

2000-07-11

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523008, 365203, 365190, 365196, 36518908, G11C 818

Patent

active

060882921

ABSTRACT:
A semiconductor memory includes a plurality of banks, a timing control circuits, and latch circuits. The timing control circuit is arranged commonly to the plurality of banks and outputs a signal for activating each bank and a signal for precharging each bank in a predetermined order at predetermined timings. Each latch circuit is arranged for each bank and latches the state of a signal output from the timing control circuit.

REFERENCES:
patent: 5036493 (1991-07-01), Nielsen
patent: 5495454 (1996-02-01), Fukuzo
patent: 5559752 (1996-09-01), Stephens, Jr. et al.
patent: 5774409 (1998-06-01), Yamazaki et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device having a plurality of banks activate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a plurality of banks activate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a plurality of banks activate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-548681