Semiconductor memory device having a plurality of banks...

Details Semiconductor memory device having a plurality of banks... Semiconductor memory device having a plurality of banks...

2000-12-29

2002-05-07

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230010, C365S063000

Reexamination Certificate

active

06385121

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory device having a plurality of banks sharing a column control unit.
2. General Background and Related Art
FIG. 1
is a block diagram of a semiconductor memory device constructed by four banks in accordance with a conventional art.
The semiconductor memory device comprises four banks
1
a
-
1
d
and column control units
2
a
-
2
d
, each arranged at an one end of the corresponding hank, for controlling the banks
1
a
-
1
d
. Each of the column control units
2
a
-
2
d
include
32
write drivers (not shown) and 32 data bus sense amplifiers (not shown).
Each of the banks
1
a
-
1
d
includes the corresponding row decoders
3
a
-
3
d
, which are arranged to the center of each bank, and 32 pairs of global data bus (not shown).
FIG. 2
is a block diagram illustrating column control units
2
a
and
2
b
for controlling two adjacent banks
1
a
and
1
b
in the block diagram of FIG.
1
. There are a number pairs of write driver WD and data bus sense amplifier DBSA. Each write driver WD drives data loaded to a global write input/output line GWIO being shared by four banks
1
a
-
1
d
and then outputs the data to a pair of global data buses GDB and /GDB of the respective banks
1
a
-
1
d
, and each data bus sense amplifier DBSA amplifies data loaded to a pair of global data buses GDB and /GDB of the respective banks
1
a
-
1
d
and outputs the data to a pair of global read input/output lines GRIO and /GRIO being shared by four banks
1
a
-
1
d.
FIG. 3
is a detailed circuit diagram of the data bus sense amplifier DBSA of the column control units
2
a
and
2
b
. The data bus sense amplifier DBSA includes differential amplifiers
4
a
and
4
b
, enabled by a data bus sense amplifier enable signal DBSAEN for sensing data loaded to a pair of global data buses GDB and /GDB. A cross-coupled amplifier
5
senses and amplifies the data enabled by the data bus sense amplifier enable signal DBSAEN and then sensed by the differential amplifiers
4
a
and
4
b
and then transmits the sensed and amplified data to a pair of global read input/output lines GRIO and /GRIO. Data bus sense amplifier DBSA includes a PMOS transistor PM
1
for equalizing output lines of the differential amplifiers
4
a
and
4
b
when the data bus sense amplifier enable signal DBSAEN is disabled. PMOS transistors PM
2
-PM
4
pre-charge and equalize the output terminal of the cross-coupled amplifier
5
with a constant level when the data bus sense amplifier enable signal DBSAEN is disabled.
FIG. 4
is a detailed circuit diagram of the write driver WD of the column control units
2
a
and
2
b
. The write driver WD includes decoding units
6
a
and
6
b
for decoding the data loaded to a global write input/output line GWIO shared by four banks
4
a
-
4
d
when a pre-charge enable signal PCGEN is disabled and a write drive enable signal WDEN is enabled.
Latch units
7
a
and
7
b
latch the decoded data from decoding units
6
a
and
6
b
. Drive units
8
a
and
8
b
transmit the latched data from the latch unit
7
a
and
7
b
to a pair of global data busses GDD and /GDB of each bank.
The write driver WD further includes a PMOS transistor PM
21
for equalizing the global data busses GDB and /GDB. PMOS transistors PM
22
and PM
23
pre-charge the global data busses GDB and /GDB with a constant level.
The conventional semiconductor memory device has
32
pairs of write drivers WD and data bus sense amplifiers DBSA having MOS devices of very large size in order to promote a transmission efficiency of banks of
1
a
-
1
b
, respectively. As a result, 128 write driver units WD and data bus sense amplifiers DBSA should be equipped, in the entire the semiconductor memory device. This is disadvantageous in that the chip area must be made to be very large and a current consumption increases.
SUMMARY
The claimed inventions feature, at least in part, a semiconductor memory device in which a plurality of banks, which are adjacent to each other, share one column control unit, thereby reducing a chip area and decreasing current consumption. A write driver in the present invention is constructed by using a cross-coupled amplifier, thereby reducing a layout area.
The column control unit is selectively connected with a plurality of banks by using a switching unit which is controlled by a control signal assembled with bank addresses. Therefore, the number of a data bus sense amplifiers and a drivers needed in the column control unit is decreased. Consequently, chip area can be reduced, speed is enhanced, and current consumption is decreased. An exemplary embodiment of a semiconductor memory device according to the inventions herein includes a plurality of memory banks wherein each memory bank has multiple pairs of global data bus for transferring data from or to itself. A plurality of column control means controls input and output of data between the memory bank and the outside devices. Each column control means is arranged between adjacent ones of the plurality of memory banks, and controls the input or output of data of the adjacent ones. Each column control means includes: 1) a plurality of write drivers, each assigned to one pair of global data bus, for transferring the data inputted from the outside devices into the memory bank; 2) a plurality of data bus sense amplifiers, each assigned to one pair of global data bus, for sensing and amplifying data from the memory bank and then outputting the amplified data toward the outside devices; and 3) a plurality of switching means for connecting one of the adjacent ones with the outside devices with the plurality of write drivers and data bus sense amplifiers.


REFERENCES:
patent: 6175532 (2001-01-01), Ooshi

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