Semiconductor memory device having a multibit parallel test func

Details Semiconductor memory device having a multibit parallel test func Semiconductor memory device having a multibit parallel test func

1990-03-28

1993-04-13

Atkinson, Charles E.

Excavating

371 211, 371 151, 371 3, G11C 2900

Patent

active

052028887

ABSTRACT:
A semiconductor memory device has a multibit parallel test function and a method of testing such a memory device. The memory device comprises a multibit parallel writing circuit (2) and a multibit parallel check circuit (3). The method comprises the steps of: inputting test data into a memory unit through an input (4) while setting the multibit parallel writing circuit (2) to the ON state by a control circuit; reading out the multibit test data from the memory unit, while setting the multibit parallel check circuit (3) to the OFF state, thereby conducting the test of the multibit parallel writing circuit (2) inputting multibit test data into the memory unit through the input, while setting the multibit parallel writing circuit (2) to the OFF state by the control circuit; and reading out the multibit test data from the memory unit, while setting the multibit parallel check circuit (3) to the ON state, thereby conducting the test of said multibit parallel check circuit (3).

REFERENCES:
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patent: 4602369 (1986-07-01), Murakami et al.
patent: 4742293 (1988-05-01), Koo et al.
patent: 4879717 (1989-11-01), Sauerward et al.
patent: 4970727 (1990-11-01), Miyawaki et al.

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