Semiconductor memory device having a hierarchical I/O structure

Details Semiconductor memory device having a hierarchical I/O structure Semiconductor memory device having a hierarchical I/O structure

2005-08-23

2005-08-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S207000

Reexamination Certificate

active

06934214

ABSTRACT:
Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

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