Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2010-03-17
2010-12-21
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185180, C257S350000
Reexamination Certificate
active
07855920
ABSTRACT:
A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.
REFERENCES:
patent: 4090254 (1978-05-01), Ho et al.
patent: 4250569 (1981-02-01), Sasaki et al.
patent: 5218217 (1993-06-01), Oda et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5712501 (1998-01-01), Davies et al.
patent: 5770881 (1998-06-01), Pelella et al.
patent: 5774411 (1998-06-01), Hsieh et al.
patent: 5784311 (1998-07-01), Assaderaghi et al.
patent: 5870329 (1999-02-01), Foss
patent: 6111778 (2000-08-01), MacDonald et al.
patent: 6621725 (2003-09-01), Ohsawa
patent: 6693326 (2004-02-01), Adan
patent: 6825524 (2004-11-01), Ikehashi et al.
patent: 7242608 (2007-07-01), Ohsawa
patent: 7257015 (2007-08-01), Ohsawa
patent: 7710785 (2010-05-01), Ohsawa
patent: 1180799 (2002-02-01), None
patent: 5678156 (1981-06-01), None
patent: 56119986 (1981-09-01), None
patent: 03171768 (1991-07-01), None
patent: 586864 (1993-12-01), None
patent: 587027 (1993-12-01), None
patent: 8213624 (1996-08-01), None
patent: 9700227 (1997-01-01), None
Hsing-jen Wann, et al., “A Capacitorless DRAM Cell on SOI Substrate”, IEEE, 1993, pp. 26.4.1-26.4.3.
Mamix R. Tack, et al., “The Multistable Charge-Controlled Memory Effect on SOI MOS Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, May 1990, pp. 1373-1382, vol. 37, No. 5.
John E. Leiss, et al., “dram Design Using the Taper-Isolated Dynamic RAM Cell”, IEEE Transactions on Electron Devices, Apr. 1982, pp. 707-714, vol. Ed. 29, No. 4.
Shigeki Tomishima, et al., “A Long Data Retention SOI-DRAM with the Body Refresh Function”, 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 198-199.
European Search Report of EP 0111965 dated Aug. 17, 2005.
Office Action and Translation of KR 10-2001-0049510 dated Aug. 29, 2004.
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Tran Andrew Q
LandOfFree
Semiconductor memory device having a floating storage bulk... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having a floating storage bulk..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a floating storage bulk... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4155661