Semiconductor memory device having a divided bit line structure

Details Semiconductor memory device having a divided bit line structure Semiconductor memory device having a divided bit line structure

1989-01-18

1990-11-13

Hecker, Stuart N.

Static information storage and retrieval

Format or disposition of elements

365174, G11C 502, G11C 1134

Patent

active

049706853

ABSTRACT:
A semiconductor memory device includes an array of memory cells arranged in rows and columns, a plurality of divided bit line pairs connecting the memory cells, the divided bit line pairs extending along a given column of memory cells, and a pair of main bit lines extending substantially parallel to the divided bit line pairs. The semiconductor memory device further comprises a plurality of sense amplifiers, each provided for two adjacent divided bit line pairs, a plurality of first switching circuit, each of which is provided for connecting each sense amplifier to either of the two adjacent divided bit line pairs, and a plurality of second switching circuit for transferring the output signal of each the sense amplifier to the pair of main bit lines.

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Taylor et al., "A 1-Mbit CMOS Dynamic Ram with a Divided Bitline Matrix Architecture," IEEE Journal of Solid State Circuits, vol. SC-20, No. 5, Oct. 85, pp. 894-902.

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