Semiconductor memory device having a decoding circuit for reduci

Details Semiconductor memory device having a decoding circuit for reduci Semiconductor memory device having a decoding circuit for reduci

1991-07-16

1994-04-05

Sikes, William L.

Static information storage and retrieval

Read only systems

Semiconductive

365185, 36523006, G11C 1700

Patent

active

053011449

ABSTRACT:
Electric field stress applied to memory cells is relieved in a semiconductor memory device. For this purpose, an X-decoder circuit applies a low level signal to a selected memory cell in a selected memory cell block of a selected memory cell matrix, and a high level signal to non-selected memory cells in the selected memory cell block, while the X-decoder circuit applies the low level signal to memory cells of non-selected memory cell blocks of the selected memory cell matrix and memory cells of non-selected memory cell matrices.

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D'Arrigo et al, "Nonvolatile Memories", IEEE International Solid-State Circuits Conference, 1989, pp. 132-133.
"Low Power Decoding Scheme For Partitioned Arrays", IBM Technical Disclosure Bulletin, vol. 29, No. 4, 1986, pp. 1533-1535.

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