Semiconductor memory device having a compact symmetrical layout

Details Semiconductor memory device having a compact symmetrical layout Semiconductor memory device having a compact symmetrical layout

1993-03-15

1994-12-13

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 68, 257903, 365156, H01L 2701

Patent

active

053731700

ABSTRACT:
A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transistor (20) resides in the first active region (44). The second driver transistor (20) has a gate electrode (55) overlying a portion of the first active region (44) and is electrically coupled to the second active region (46). A thin-film load transistor (18) resides over the first active region (44), the thin-film load transistor (18) has a thin-film channel layer (23) that overlies, and is aligned with, the gate electrode (55) of the second driver transistor (20). A second portion of the thin-film channel layer (23) extends away from the first active region (44) to form a Vcc node (36). A Vcc interconnect layer (82) overlies the thin-film load transistors and the driver transistors. The Vcc interconnect layer (82) is electrically isolated from the thin-film gate electrode and electrically contacts the second portion of the thin-film channel layer (23) at Vcc node (36). A thin-film load transistor (22) having structure corresponding with thin-film load transistor (20) resides over the second active region (46).

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patent: 5326989 (1994-07-01), Muragishi
Tsutsumi et al., "A High Performance SRAM Memory Cell with LDD-TFT Loads," 1991 Symp. on VLSI Technology, Digest of Technical Papers, pp. 23-24.

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