Semiconductor memory device having a column select line...

Details Semiconductor memory device having a column select line... Semiconductor memory device having a column select line...

2002-01-18

2002-10-15

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011

Reexamination Certificate

active

06466509

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to those providing a faster column-related operation.
2. Description of the Background Art
In recent years, there has been a demand for increasing data in capacity and also communicating the data rapidly and a multi input and output and multibank, logic embedded dynamic random access memory (eDRAM) has accordingly been generally used.
FIG. 24
represents a relationship between a memory bank BK and column select lines CSL_ODD<
1
:
0
> and CSL_EVEN<
1
:
0
>. Note that hereinafter for a plurality of bits <Z:
0
>,
0
to Z are applied, wherein Z represents a natural number.
Memory bank BK includes a row decoder
1004
, a sense amplifier bands SAG(
0
)-SAG(
4
) (hereinafter generally referred to as a sense amplifier band SAG), and memory blocks MBL(
0
)-MBL(
3
) (hereinafter generally referred to as a memory block MBL). Each memory block MBL is arranged between sense amplifier bands SAGs. When a signal is input from column select lines CSL_ODD<
1
:
0
> and CSL_EVEN<
1
:
0
> to each sense amplifier band SAG a signal is input to each sense amplifier band SAG via a driver DRI. Each sense amplifier band SAG includes a plurality of bit line select circuits BSLs and it is activated by any signal input from column select lines CSL_ODD<
1
:
0
> and CSL_EVEN<
1
:
0
> to electrically connect each bit line pair and input/output line pairs IO(
0
), /IO(
0
) to IO(m), /IO(m) respectively (hereinafter generally referred to as an input/output line pair IO, /IO) to read or write data, wherein m represents a natural number. Each input/output line pair IO and /IO is arranged orthogonal to each memory block MBL.
A description will now be provided of a sense amplifier block
1100
including bit line select circuit BSLs of their respective sense amplifier bands SAG(
0
) and SAG(
1
) at the bottom. The other sense amplifier blocks are similarly configured and thus will not be described specifically.
FIG. 25
shows a circuit configuration of sense amplifier block
1100
.
Each sense amplifier band SAG has a circuit configuration in a shared SA system and sense amplifier block
1100
includes an input/output line pair /IO(m) and IO(m), bit line pairs BL
0
, /BL
0
to /BL
3
, BL
3
, hereinafter generally referred to as a bit line pair BL and /BL, a sense amplifier circuit S/A, and column select lines CSL_ODD
1
, CSL_ODD
0
, CSL_EVEN
1
and CSL_EVEN
0
.
Column select lines CSL_ODD
1
and CSL_ODD
0
connect with bit line select circuits BSL
0
, BSL
1
, respectively. Each bit line pair BL, /BL is connected to each bit line select circuit BSL via sense amplifier circuit S/A. Furthermore, bit line select circuit BSL
0
and BSL
1
are connected to input/output line pair IO(m), /IO(m) respectively.
FIG. 26
shows a circuit configuration of bit line select circuits BSL
0
and BSL
1
.
Bit line select circuits BSL
0
and BSL
1
include N channel MOS transistors NT
1
, NT
2
, respectively, operating as a gate circuit, and when bit line select circuit BSL
0
is activated by a signal on column select line CSL_ODD
1
and n channel MOS transistor NT
1
turns on, input/output line pair IO(m), /IO(m) and bit line pair BL
3
, /BL
3
are electrically coupled together. When bit line select circuit BSL
1
is activated by a signal on column select line CSL_ODD
0
and N channel MOS transistor NT
2
turns on, input/output line pair IO(m), /IO(m) and bit line pair BL
1
, /BL
1
are electrically coupled together. Thus one of the signals on column select lines CSL_ODD
1
and CSL_ODD
0
input activates each bit line select circuit BSL connected to the respective signal lines and data is thus read or written.
Reference will again be made to
FIG. 24
to consider an example with a plurality of memory banks BKs.
Memory bank BK shares column select lines CSL_EVEN<
1
:
0
> and CSL_ODD<
1
:
0
>. Column select line CSL_EVEN<
1
:
0
>, connected to odd-numbered sense amplifier bands SAGs, has two drivers DRIs connected for a unit memory bank BK, and column select line CSL_ODD<
1
:
0
>, connected to even-numbered sense amplifier bands SAGs, has three drivers DRIs connected per a unit memory bank BK. This results in a ratio in load of two to three and column select line CSL_ODD<
1
:
0
> is larger in load than column select line CSL_EVEN<
1
:
0
>, resulting in a delayed timing of a signal to be transmitted.
FIG. 27
is timing plots in a write operation.
As shown in
FIG. 27
, in the write operation input/output line pair IO and /IO is driven in response to data to high and low levels, respectively. During that period, bit line pair BL, /BL must be selected in response to column select lines CSL_EVEN<
1
:
0
> and CSL_ODD<
1
:
0
> to write data, although if there is a difference in tiling between column select lines CSL_EVEN<
1
:
0
> and CSL_ODD<
1
:
0
> that is associated with a difference in load, input/output line pair IO, /IO must be driven continuously throughout a period satisfying the difference in timing of the two. Thus a column cycle (tC) cannot be reduced and rapid column-related operation cannot be achieved.
FIG. 28
shows another configuration different from that of
FIG. 24
, showing a memory bank configuration effecting a column select operation in response to a predecoded signal.
FIG. 28
schematically shows memory banks #
0
-#
3
and a column decode circuit
2
a.
Memory banks #
0
-#
3
are similar in configuration and memory bank#
0
will be described representatively.
Memory bank#
0
includes memory blocks M
0
-M
3
(memory banks #
1
-#
3
include memory blocks M
4
-M
15
) and sense amplifier bands SAG#
0
a
to SAG#
0
e
(hereinafter generally referred to as a sense amplifier band SAG#
0
) and memory cell arrays
10
-
13
are each arranged between two of sense amplifier bands SAG#
0
a
to SAG#
0
e
. Column decode circuit
2
a
includes a column predecode circuit
300
, a block select line BS<
15
:
0
> corresponding to each of memory blocks M
0
-M
15
, hereinafter generally referred to as a block select line BS), a bank select line SBA<
3
:
0
> corresponding to each of memory banks #
0
-#
3
, hereinafter generally referred to as a bank select line SBA), column select lines CSLER<
3
:
0
> and CSLOR<
3
:
0
> shared by all memory banks and dedicated to reading data, (hereinafter generally referred to as column select lines CSLER and CSLOR), column select lines CSLEW<
3
:
0
> and CSLOW<
3
:
0
> shared by all memory banks and dedicated to writing data (hereinafter generally referred to as column select lines CSLEW and CSLOW), CSL decode circuits
100
a
-
100
e
(hereinafter generally referred to as a CSL decode circuit
100
), and block select latch circuits
200
a
-
200
d
(hereinafter generally referred to as a block select latch circuit
200
). While herein column select lines CSLER and CSLOR or column select lines CSLEW and CSLOW are adapted to have an 8-bit configuration, they are not limited thereto and may be of n
1
bit equal to or grater than eight bits, wherein n
1
represents a natural number.
FIG. 29
shows circuit configurations of column predecode circuit
300
.
In FIG.
29
(A) a column address NCA<
2
:
0
> is a signal representing a column address CA<
2
:
0
> that is inverted by an inverter INV.
FIG.
29
(B) shows a timing generation circuit GT receiving clock signals Read. CLK and Write. CLK exclusively for read and write operations to generate timing signals RTM and WTM, respectively.
FIG.
29
(C) shows a data reading logic unit generating a signal selecting any one of column select lines CSLER
0
-CSLER
3
and CSLOR
0
-CSLOR
3
. While herein a column select line is selected for reading data, also for writing data, timing signal WTM for the write operation is received and one of writing column select lines CSLEW<
3
:
0
> and CSLOW<
3
:
0
> is selected.
AND circ

Affiliated with

Also associated with

Rating

Semiconductor memory device having a column select line... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having a column select line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having a column select line... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2936518