Semiconductor memory device having a CMOS decoding circuit

Details Semiconductor memory device having a CMOS decoding circuit Semiconductor memory device having a CMOS decoding circuit

1992-08-19

1994-05-10

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518901, 36518905, 307463, 307449, 307445, 307443, G11C 700, G11C 800

Patent

active

053114795

ABSTRACT:
The semiconductor memory device receives a first and a second pairs of input signals. Each of the pairs has a first and a second address signals which are complementary and substantially in phase. The semiconductor memory device comprises a pre-decoder for receiving the first and second pairs of input signals and outputting a first and second pre-decode signals. The first and second pre-decode signals are complementary signals and are substantially in phase with each other. The pre-decoder comprises a NAND gate for receiving the first input signals of the first and second pairs and outputting the first pre-decode signal and a NOR gate for receiving the second input signals of the first and second pairs and outputting the second pre-decode signal. The NOR gate and the NAND gate are electrically isolated from each other. The semiconductor memory device further comprises a row decoder coupled to the pre-decoder and word lines for selecting one of the word lines in response to the pre-decode signals and a memory array coupled to the row decoder through the word lines.

REFERENCES:
patent: 4281397 (1981-07-01), Neal et al.
patent: 4344005 (1982-08-01), Stewart
patent: 4797576 (1989-01-01), Asazawa
patent: 4951259 (1990-08-01), Sato et al.
patent: 5132933 (1992-07-01), Schreck et al.

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