Semiconductor memory device having a burst mode

Static information storage and retrieval – Addressing – Byte or page addressing

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Details

36518902, 365203, G11C 800

Patent

active

060672749

ABSTRACT:
A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; and a row selector for selecting one of the rows of the memory cell array in accordance with an input address signal, the semiconductor memory device having a burst mode for sequentially accessing one row of memory cells. The memory cell array includes a plurality of groups each including at least one column of memory cells, and wherein the semiconductor memory device further includes: a column selector for simultaneously selecting all of the columns in each group in accordance with the input address signal; and at least two precharge circuits for precharging bit lines associated with the columns in each group selected by the column selector.

REFERENCES:
patent: 5357477 (1994-10-01), Matsumoto et al.
patent: 5703828 (1997-12-01), Park et al.
patent: 5748561 (1998-05-01), Hotta
patent: 5751657 (1998-05-01), Hotta

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