Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2003-02-04
2003-12-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185220
Reexamination Certificate
active
06657891
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-347797, filed Nov. 29, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device capable of storing, for example, 2 bits or more of data.
2. Description of the Related Art
A nonvolatile semiconductor memory device capable of storing mutivalued data, such as a NAND flash memory using EEPROM, has been proposed (U.S. Pat. No. 6,178,115).
In a NAND flash memory where a plurality of cells are arranged in a matrix, all of or half of the cells arranged in the direction of row are selected simultaneously. Data is written into or read from the selected cells in unison. Specifically, the selected cells are connected to corresponding bit lines. A latch circuit for holding the write and read data is connected to each bit line. Data is written or read by using the latch circuit.
This type of nonvolatile semiconductor memory device has been miniaturized so significantly that the spacing between adjacent cells in the row direction and the column direction is very narrow. As the distance between adjacent cells becomes shorter, the capacitance between the floating gates of adjacent cells (FG-FG capacitance) becomes larger. This causes the following problem: the threshold voltage Vth of a cell written into previously varies according to the data in an adjacent cell written into later due to the FG-FG capacitance. In the case of a mutivalued memory that stores a plurality of data (k bits) in a single cell, it has a plurality of threshold voltages. Therefore, it is necessary to control the distribution of a threshold voltage per data very narrowly, which causes the following significant problem: the threshold voltage varies according to the data in the adjacent cells. Therefore, a nonvolatile semiconductor memory device capable of preventing the threshold voltage from varying with the data in the adjacent cells has been demanded.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix, each storing n-valued data (n is a natural number equal to or larger than 2); and a write circuit which writes data into each of the memory cells and which, before storing next at least one-valued data into a first memory cell in which j-valued data (j<n) has been stored in the memory cell array, writes j or less-valued data into at least one of the memory cells adjacent to the first memory cell.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array which has at least one first memory cell arranged in a matrix and at least one second memory cell selected simultaneously with the first memory cell, the first memory cell storing n-valued data (n is a natural number equal to or larger than 2); and a write circuit which, when writing next at least one-valued data into the first memory cell in which j-valued data (j<n) in the memory cell array has been stored, writes data to change the logic level of the second memory from a first logic level to a second logic level.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell which stores k bits (k is a natural number equal to or larger than 2); a first storage circuit which stores an input data; a second storage circuit which stores the data read from the memory cell or the input data; and a control circuit which, in a write operation, holds or changes the data in the first storage circuit or the data in the second storage circuit on the basis of the data stored in the memory cell and which, in the middle of a write operation, inputs next write data to the first storage circuit, when the data stored in the first storage circuit becomes unnecessary to the write operation.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array which has at least one first memory cell arranged in a matrix and at least one second memory cell selected simultaneously with the first memory cell, the first memory cell storing k (k is a natural number equal to or larger than 2) bits of data; a write circuit which, before storing next at least one bit of data into the first memory cell in which i bits (i<k) of data has been stored in the memory cell array, writes i or less bits of data into at least one of the memory cells adjacent to the first memory cell and, when writing one bit of data into the first memory cell, writes data into the second memory cell; and a read circuit which, when outputting the data read from the first memory cell, controls the logic level of the data to be outputted on the basis of the data stored in the second memory cell.
REFERENCES:
patent: 5428569 (1995-06-01), Kato et al.
patent: 5986933 (1999-11-01), Takeuchi et al.
patent: 6028794 (2000-02-01), Nakai et al.
patent: 6288935 (2001-09-01), Shibata et al.
patent: 6373746 (2002-04-01), Takeuchi et al.
Shibata Noboru
Tanaka Tomoharu
Hogan & Hartson LLP
Le Vu A.
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