Semiconductor memory device for storing multilevel data

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185240

Reexamination Certificate

active

07471559

ABSTRACT:
In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.

REFERENCES:
patent: 6091631 (2000-07-01), Kucera et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 6847550 (2005-01-01), Park
patent: 6847555 (2005-01-01), Toda
patent: 7224614 (2007-05-01), Chan
patent: 2004-192789 (2004-07-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor memory device for storing multilevel data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device for storing multilevel data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device for storing multilevel data will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4034855

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.