Semiconductor memory device for stably controlling power...

Details Semiconductor memory device for stably controlling power... Semiconductor memory device for stably controlling power...

2007-08-28

2007-08-28

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080, C365S233500

Reexamination Certificate

active

11320340

ABSTRACT:
The present invention relates to a semiconductor memory device. When a device exits from power mode, after a time until an instruction/address receive control signal substantially turns on or off an address and instruction input buffer unit and a time until the address and instruction buffer unit is turned on to synchronize an external command signal to an internal clock signal are compensated for, an internal clock-generating control signal for controlling generation of the internal clock signal is sensed at a high phase of a buffered clock signal and is generated at a low phase of the buffered clock signal. Further, when a device enters power mode, an internal clock-generating control signal for controlling generation of an internal clock signal is sensed at a high phase of a buffered clock signal and is then generated at a low phase of the buffered clock signal.

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