Semiconductor memory device for reading information in...

Details Semiconductor memory device for reading information in... Semiconductor memory device for reading information in...

2000-02-10

2001-11-06

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S204000

Reexamination Certificate

active

06314015

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically to a memory array for reading information in memory cells using bit lines and virtual GND lines.
2. Description of the Related Art
There is a conventional system for reading information in memory cells of an MROM (Mask Read Only Memory) using bit lines and virtual GND lines.
FIG. 6
is a conceptual view illustrating a configuration of a memory array
600
in a conventional MROM operating in such a system.
A memory array
600
shown in
FIG. 6
includes a plurality of bit lines
601
and a plurality of virtual GND lines
602
. A MOSFET
603
or a MOSFET
603
A is connected between each pair of adjacent bit line
601
and virtual GND line
602
. The MOSFETs
603
and
603
A store binary information in the memory array
600
as described later and will be referred to as “memory cell transistors”, hereinafter. In
FIG. 6
, the memory cell transistor
603
is a selected memory cell transistor, from which information is to be read. A word line
605
is provided perpendicular to the bit lines
601
and the virtual GND lines
602
. The word line
605
is connected to a gate electrode
604
of each of the memory cell transistors
603
and
603
A. A plurality of memory cell transistors
603
and
603
A are connected to one word line
605
, thus improving the space efficiency of the memory cell. The bit line
601
connected to the selected memory cell transistor
603
is connected to a charging circuit
1
and a sensing circuit
2
, and the virtual GND line
602
connected to the selected memory cell transistor
603
is grounded. The charging circuit
1
is one exemplary device for charging the bit line
601
.
The memory array
600
is produced so as to include the following two types of memory cell transistors. One type of memory cell transistors have a relatively high threshold level; i.e., are not turned ON when a certain voltage is applied by the word line
605
through the gate electrode
604
(OFF transistors). The other type of memory cell transistors have a relatively low threshold level; i.e., are turned ON when a certain voltage is applied by the word line
605
through the gate electrode
604
(ON transistors). Thus, binary information is stored in the memory array
600
.
In the conventional memory array
600
, the information is read in the following manner. The bit line
601
connected to the memory cell transistor
603
is charged by the charging circuit
1
, and the virtual GND line
602
connected to the memory cell transistor
603
is grounded. In this potential state, the difference between the ON transistors and the OFF transistors is read by the sensing circuit
2
. Thus, the information stored in the memory cell transistor
603
is determined to be ON or OFF.
One generally known system for reading information in such a memory array at a high speed is a hierarchical bit line system. A memory array operating in this system includes a main bit line, a sub bit line, and a bank transistor for connecting the main bit line and the sub bit line.
The main bit line mainly is formed of a metal layer, and a sub bit line mainly is formed of a diffusion layer. The diffusive layer acts as a source and a drain of each memory cell transistor. A group of memory cells respectively having gate electrodes connected to word lines WL
1
through WLn in a bank transistor is referred to as a bank. In order to improve the space efficiency of the memory cell, one main bit line is connected to a plurality of sub bit lines through the bank transistor on a bank-by-bank basis. High speed reading is realized by accessing the memory cell through the main bit line on a bank-by-bank basis.
FIG. 7
is a configuration of a memory array circuit
700
of the hierarchical bit line system.
As shown in
FIG. 7
, the memory array circuit
700
includes a memory array
40
, which includes a plurality of memory cell transistors arranged in an array. In more detail, the memory array
40
includes a plurality of word lines (e.g., word lines WL
0
through WLn). Each word line (e.g., word line WL
0
) is connected to a gate of each memory cell transistor of a plurality of memory cell transistors (e.g., memory cell transistors M
0
through M
14
). A plurality of bit lines and a plurality of virtual GND lines are provided perpendicular to the word lines. In
FIG. 7
, the main bit lines are indicated by MB
0
, MB
2
, MB
4
, MB
6
and MB
8
; and the virtual GND lines are indicated by MB
1
, MB
3
, MB
5
and MB
7
. Drains of the memory cell transistors connected to one word line are respectively connected to sources of the adjacent memory cell transistors. Accordingly, the memory cell transistors are connected in series. The sub bit lines are connected between a source of each memory cell transistor and a drain of an adjacent memory cell transistor.
The main bit line MB
2
and the virtual GND line MB
3
will be described, hereinafter. The main bit line MB
2
is connected to sub bit lines SB
2
and SB
4
. The sub bit line SB
2
is connected to a drain of a memory cell transistor M
1
and a source of the memory cell transistor M
2
through a bank transistor BK
1
-
2
. The sub bit line SB
4
is connected to a drain of a memory cell transistor M
3
and a source of the memory cell transistor M
4
through a bank transistor BK
1
-
1
. Since a gate of the bank transistor BK
1
-
1
is connected to a bank selection line BKL
2
, the bank transistor BK
1
-
1
is selected by the bank selection line BKL
1
. Since a gate of the bank transistor BK
1
-
2
is connected to a bank selection line BKL
2
, the bank transistor BK
1
-
2
is selected by the bank selection line BKL
2
. A drain of the memory cell transistor M
2
and a source of the memory cell transistor N
3
are connected to a sub bit line SB
3
.
The main bit line MB
2
is connected to, for example, a block selection circuit
30
, a charging and GND selection circuit
10
and a charging and sensing circuit
20
. In more detail, a current from the main bit line MB
2
is input to the charging and GND selection circuit
10
through a transistor TR
1
of the block selection circuit
30
. The current is then divided into two so as to be sent separately through transistors TR
2
and TR
3
. The divided currents are input to the charging circuit
1
in the charging and sensing circuit
20
. The current sent through the transistor TR
3
in the charging and GND selection circuit
10
is detected by a sensing circuit
50
in the charging and sensing circuit
20
. Gates of the transistors TR
1
, TR
2
and TR
3
are respectively connected to lines BLOCKSEL
1
, BSEL
1
and BSEL
2
and thus controlled.
A drain of the memory cell transistor M
4
and a source of a memory cell transistor M
5
are connected to a sub bit line SB
5
. The sub bit line SB
5
is connected to a virtual GND line MB
3
through a bank transistor BK
3
-
2
. A gate of the bank transistor BK
3
-
2
is connected to a bank selection line BKL
3
. A current from the virtual GND line MB
3
is input to the charging and GND selection circuit
10
through a transistor TR
4
of the block selection circuit
30
. The current is then divided into two so as to be sent separately through transistors TR
5
and TR
6
. The current sent through the transistor TR
5
is grounded in the charging and GND selection circuit
10
. The current sent through the transistor TR
6
is input to the charging circuit
1
in the charging and sensing circuit
20
. Gates of the transistors TR
4
, TR
5
and TR
6
are respectively connected to lines BLOCKSEL
1
, VGSEL
1
and VGSEL
2
and thus controlled.
The configuration regarding the other main bit lines and virtual GND lines are substantially the same as the configuration regarding the main bit line MB
2
and the virtual GND line MB
3
, and thus will not be described herein.
The charging and GND selection circuit
10
and the charging and sensing circuit
20
can be connected to a plurality of block selection circuits
30
.
The memory array circuit
700
operates in the following

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