Semiconductor memory device for multi-bit or multi-bank architec

Details Semiconductor memory device for multi-bit or multi-bank architec Semiconductor memory device for multi-bit or multi-bank architec

1997-01-22

1998-07-14

Zarabian, A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 63, G11C 800

Patent

active

057814953

ABSTRACT:
In a semiconductor memory device, global column-select lines are provided for selecting specific memory-cell arrays in accordance with select signals, and a pair of global input/output signal line is provided for each memory-cell array and connected to a pair of local input/output signal lines associated with the memory-cell array on a one-to-one basis to implement a multi-bank architecture. Alternatively, each pair of local input/output signal lines is divided into pairs of partial local input/output signal lines which are each connected to a pair of global input/output signal lines on a one-to-one basis. A memory-cell architecture is provided which has a number of data buses corresponding to an increased number of divided memory-cell arrays or memory banks to meet demands for a multi-bank and multi-bit semiconductor memory device.

REFERENCES:
patent: 5471430 (1995-11-01), Sawada
patent: 5603009 (1997-02-01), Konishi

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