Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1998-04-02
2001-06-19
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S063000
Reexamination Certificate
active
06249474
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to a semiconductor memory device, and in particular to a semiconductor memory device having a multi-bit architecture or a multi-bank architecture.
BACKGROUND ART
FIG. 12
is a diagram showing an architecture of a memory-cell array in a dynamic random-access memory (DRAM) as a typical conventional semiconductor memory device. As shown in the figure, memory-cell arrays (or memory banks)
206
each comprising a number of memory cells laid out to form a matrix are separated from each other in a bit-line direction by sense-amplifier units
207
. The memory-cell arrays
206
are separated in a word-line direction by a word-line shunting area
208
in the case of a word-line shunt system or by a sub-word driver area
208
in the case of a split word-line architecture.
Data is read out and latched in the sense-amplifier units
207
. Column-select lines (CSL)
209
are activated in accordance with a column address, causing the data to be output from the sense-amplifier units
207
to pairs of local I/O lines
210
. The pairs of local I/O lines
210
are connected to a pair of global I/O lines
211
which is located on the word-line shunting area or the sub-word driver area
208
to form a data route in a read/write operation.
A switch
212
is provided between each of the pairs of local I/O lines
210
and the pair of global I/O lines
211
. Only a single switch
212
associated with a selected memory-cell array
206
is turned on. Normally, the switch
212
is located at the intersection of the sense-amplifier unit
207
and the word-line shunting area or the sub-word driver area
208
. In a CSL system, the pair of local I/O lines
210
associated with a selected memory-cell array
206
is connected to the pair of global I/O lines
211
. If the switches
212
are not provided, all the pairs of local I/O lines
210
are connected to the pair of global I/O lines
211
, increasing the load on a data bus. In addition, it is generally necessary to set the precharge potentials of selected pairs of local I/O lines
210
and deselected pairs of local I/O lines
210
at different values from the access-speed point of view.
In recent years, there has been a trend of increasing the number of bits per word to keep up with increases in capacity. Demands for DRAMs with an x32/x64/x128 word structure are anticipated. Demands for multi-bank and multi-bit specifications are also foreseen for synchronous DRAMs. To meet such demands, it is necessary to incorporate a number of data buses from memory-cell arrays. In this case, it is necessary to design architectures of memory-cell arrays and data buses that do not require an increase in memory-cell-array area, that reduce the number of activated memory-cell arrays by as many as possible, and that reduce the amount of consumed current at the same time
Meeting such demands with a memory-array architecture like the one shown in
FIG. 12
would increase the loads connected to the column-select lines and the global I/O signal lines. In addition, the memory-architecture cannot sufficiently keep up with increases in bit count and memory-bank count. The present invention addresses these problems.
DISCLOSURE OF THE INVENTION
It is thus an object of the present invention to provide a semiconductor memory device that has memory-cell arrays scalable for conversion into a multi-bit or a multi-bank architecture. In particular, it is an object of the present invention to provide a preferred semiconductor memory device that can be implemented as a DRAM having a multi-bit architecture or a DRAM having a multi-bank architecture.
According to one aspect of the present invention, a semiconductor memory device comprises a plurality of memory-cell arrays each of which includes a plurality of memory cells arranged in a matrix form. A plurality of sense amplifiers is associated with each column of each memory-cell array. A plurality of column-select lines extends through the memory-cell arrays, each line in a column. Each column-select lines is connected to one of the sense amplifiers in the column in accordance with a column-select signal. A plurality of global input/output signal line pairs extends through the memory-cell arrays each in a column, and is connected commonly to the sense amplifiers in the column of the memory-cell arrays.
In another aspect of the present invention, in the semiconductor memory device, each global input/output signal line pair extends through the memory-cell arrays in a column and is disposed along the column on an upper layer of the plurality of memory cells arranged in the memory-cell array.
According to another aspect of the present invention, a semiconductor memory device comprises a plurality of memory-cell arrays each including a plurality of memory cells in a matrix form. A plurality of sense amplifiers is associated with each column of the memory-cell arrays. A plurality of column-select lines extends through the memory-cell arrays each in a column, and each column-select line is connected electrically to one of the sense amplifiers in the column in accordance with a column-select signal. A plurality of local input/output signal line pairs is provided, each of which is commonly connected to the sense amplifiers in each memory-cell array. A plurality of global input/output signal line pairs extends through the memory-cell arrays and disposed corresponding to each local input/output signal line pair. Each global input/output signal line pair is connected to the corresponding local input/output signal line pairs associated with each memory-cell array.
In another aspect of the present invention, in the semiconductor memory device, each global input/output signal line pair extends through the memory-cell arrays in each column, and is connected to each local input/output signal line pair associated with the memory-cell array on a one-to-one basis.
In another aspect of the present invention, in the semiconductor memory device, each global input/output signal line pair extends through the memory-cell arrays in each column, and is disposed along the column on an upper layer of the plurality of memory cells arranged in the memory-cell array.
In another aspect of the present invention, in the semiconductor memory device, each column-select line is connected commonly to the sense amplifiers on the same column in the memory-cell arrays.
In another aspect of the present invention, in the semiconductor memory device, each column-select line is selectively connected electrically to one of the sense amplifiers on the same column in the memory-cell arrays in accordance with a column-select signal.
In another aspect of the present invention, in the semiconductor memory device, each local input/output signal line pair is divided into a plurality of partial local input/output signal line pairs, and each global input/output signal line pair is connected to each partial local input/output signal line pair on a one-to-one basis.
In another aspect of the present invention, in the semiconductor memory device, each memory-cell array is divided into partial memory-cell arrays, and each partial memory-cell array is connected to each global input/output signal line pair on a one-to-one basis.
In another aspect of the present invention, for each semiconductor memory device as stated above, a conductive lead structure is provided on said memory-cell arrays. The conductive lead structure comprises a first layer of word-lines, a second layer of column-select lines and global input/output signal line pairs, and a third layer of power-supply lines.
In another aspect of the present invention, in each of the semiconductor memory device as stated above, a conductive lead structure is provided on said memory-cell arrays. The conductive lead structure comprises a first layer of the word-lines, a second layer of column-select lines and power-supply lines, and a third layer of global input/output signal line pairs.
Additional advantages and other features of the invention are set forth in the following description and some wi
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Zarabian A.
LandOfFree
Semiconductor memory device for multi-bit or multi-bank... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device for multi-bit or multi-bank..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device for multi-bit or multi-bank... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2469664