Semiconductor memory device for low power consumption

Static information storage and retrieval – Powering

Reexamination Certificate

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C365S189110, C365S203000

Reexamination Certificate

active

11146513

ABSTRACT:
A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

REFERENCES:
patent: 6519191 (2003-02-01), Morishita
patent: 6791895 (2004-09-01), Higeta et al.
patent: 6816418 (2004-11-01), Hidaka
patent: 2001/0001598 (2001-05-01), Narui et al.
patent: 2003/0147272 (2003-08-01), Joshi et al.

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