Semiconductor memory device for inputting/outputting data...

Details Semiconductor memory device for inputting/outputting data... Semiconductor memory device for inputting/outputting data...

2000-02-29

2001-07-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030, C365S194000

Reexamination Certificate

active

06269048

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device (memory) for inputting/outputting data through a common terminal and outputting data in synchronism with clock or, in particular, to a synchronous dynamic random access memory (SDRAM), comprising a plurality of banks of memory cells, for performing an internal operation in synchronism with the clock generated from an external clock source and outputting data in synchronism with the clock.
A DRAM with a high-speed page mode is used as a main memory for the computer. Various DRAMs intended for higher speed have been proposed. An asynchronous DRAM, for example, includes an EDO (extended data out) mode or a burst EDO mode improved from the high-speed page mode, while a synchronous DRAM includes a SDRAM. The invention relates to a synchronous memory, or in particular to a SDRAM. An explanation will be given below with reference to the SDRAM.
FIG. 1
is a block diagram showing a general configuration of a SDRAM. As shown in
FIG. 1
, a DRAM core having an array of memory cells is configured with four banks
11
-
0
to
11
-
3
. This configuration with a plurality of banks is intended to improve the data transfer rate by employing a method called interleaving for accessing the banks on rotation. A clock buffer
21
generates an internal clock clkz in response to an external clock, and supplies the internal clock to various parts. Each part operates in synchronism with the internal clock clkz. A command decoder
22
generates a signal used for internal control from the external control signals such as a chip select signal (/CS), /RAS, /CAS, /WE supplied from an external source. An address buffer
23
is a circuit for receiving an address signal Add input from an external source. A bank select circuit
24
is for generating a bank select signal bnk#z from a portion of the address signal Add. A control signal generating circuit
25
generates a control signal applied to the banks based on the control signal from the command decoder
22
and the bank select signal bnk#z. The SDRAM has various operation modes, one of which is designated by the address signal under a predetermined state of the external control signal. A mode register
26
stores this address signal and outputs a signal indicating a mode. A row address constituting a part of the address signal is supplied directly as a row address of the bank. In the SDRAM, a predetermined number of words (burst length) are continuously read from a given address. Column address counters
27
,
28
receive the remaining column addresses of the address signal, generate continuous column addresses at high speed and supply them as the column addresses of the bank at the time of the read operation according to the prevailing mode. A burst length control circuit
29
performs the control operation for reading the data of burst length continuously in burst mode. A latency control circuit
30
is for controlling the /CAS latency (CL). CL is the number of clocks from the input of /CAS to the time when the first data is read, and can be designated in the SDRAM. The latency control circuit
30
performs the control operation for starting the data output with a designated CL.
A column bank status signal generating circuit
31
generates a column bank status signal cras#z indicating whether the column signal is activated or not based on the internal activation signal actpz generated by a command decoder
22
and the bank select signal bnk#z (# indicates the bank number as in the following description). A read status signal generating circuit
32
, on the other hand, generates a read status signal readz in accordance with the latency signal lq#z which is in turn generated in accordance with the burst length and CL. A column activation signal generating circuit
33
generates an output period signal csex indicating the period during which an output clock outpz is generated from the signals cras#z and readz. An output clock buffer
34
generates an output clock outpz from the signal csex and the clock CLK input from an external source. A FIFO
35
is a part for temporarily holding the data read from the banks, and an output circuit
36
sequentially outputs the data held in the FIFO
35
, in accordance with the output clock outpz. An output DQ is output to the same terminal by way of which the write data is input, and therefore the output of the output circuit
36
assumes a high impedance (Hi-Z) status upon complete output of the data.
A general configuration of the SDRAM was described above. The configuration will not be described in more detail, except for the parts related to the invention which include the column banks status signal generating circuit
31
, the read status signal generating circuit
32
, the column activation signal generating circuit
33
, the output clock buffer
34
, the FIFO
35
and the output circuit
36
, and which will be described below with reference to the drawings.
FIG. 2
is a circuit diagram showing the column bank status generating circuit
31
. As described above, the signal actpz is an internal activation signal generated by the command decoder
22
, the signal bnk#z is a bank select signal, the signal apre#x is a signal related to an auto precharge command, and the signal dacpz is called a PRE and PALL command signal which is used for the reset operation with the signal a
10
z. The column bank status signal cras#z output from this circuit is activated by receiving the signals actpz and bnk#z and continues to be output during the bank active period. In the case of a command with auto precharge, a pulse for reducing the signal apre#x to a “low” state is output upon complete reading of a burst, by an interrupt of the burst or an interrupt by accessing other banks. Then, the latch is inverted for resetting.
When interrupted by a write command into a different bank in the read operation with a precharge, though a command input not permitted, the signal apre#x becomes “low” and so does the signal cras#z. At the same time, the signals cras#z of other banks also become “low”.
FIG. 3
is a circuit diagram of the read status signal generating circuit
32
, and
FIG. 4
is a time chart showing the operation of the same circuit. A signal cmcpz is a clock for columns, a signal sttx is for resetting the device at the time of starting, and a signal wrtcz becomes “high” when the write command is input. Only the signal lq
0
z is output when CL is 2, and the signals lq
0
z and lq
1
z are output when CL is 3. The signals lq
0
z, lq
1
z have a period “high” as long as the burst length, and the rise timing thereof corresponds to the CL, respectively. When CL is 2, the read status signal readz output becomes “high” in response to the rise of the signal lq
0
z, which is delayed by one clock in a D-type flip-flop
40
, and the signal readz becomes “low” with the fall of the signal lq
0
z. When CL is 3, on the other hand, the signal readz becomes “high” in response to the rise of the signal lq
0
z, and the signal lq
1
z is delayed by one clock in the D-type flip-flop
40
, so that the signal readz becomes “low” with the fall thereof. Thus, the read status signal readz is a signal indicating a period longer by one clock than the data output period.
FIG. 5
is a diagram showing a circuit configuration of the FIFO circuit
35
. In the SDRAM, data are read by pipelining, while the data are output in synchronism with the clock. For this purpose, the FIFO circuit
35
, in which the data read out from the banks are temporarily stored and data are read out in the order of storage in synchronism with the clock, is provided. The signal rdrv#z designates a read data bus drive signal, and the signal ird#x/z is a read data. An input pointer counter
41
resets all the input pointers to “low” and the counter to 0 when the read status signal readz is “low”. When the signal readz is “high”, on the other hand, the pointer is enabled. The output pointer counter
42
, on the other hand, is reset to 0 w

Affiliated with

Also associated with

Rating

Semiconductor memory device for inputting/outputting data... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device for inputting/outputting data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device for inputting/outputting data... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2568124