Semiconductor memory device for guaranteeing reliability of...

Details Semiconductor memory device for guaranteeing reliability of... Semiconductor memory device for guaranteeing reliability of...

2009-06-30

2011-11-01

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S233130

Reexamination Certificate

active

08050136

ABSTRACT:
A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.

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patent: 7590211 (2009-09-01), Burney
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patent: 1020030087902 (2003-11-01), None
patent: 1020060111016 (2006-10-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Nov. 30, 2010.

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