Semiconductor memory device for controlling memory banks

Details Semiconductor memory device for controlling memory banks Semiconductor memory device for controlling memory banks

2001-12-27

2003-07-01

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080

Reexamination Certificate

active

06587391

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bank control circuit in a Rambus DRAM capable of reducing circuit area by disposing one control circuit and one address latch circuit in every two banks.
2. Description of the Related Art
FIG. 1
is a block diagram of a conventional Rambus DRAM comprising: memory blocks
10
including an upper and a lower memory block units
12
,
14
comprising
16
memory banks respectively; an upper and a lower series/parallel shifter units
16
,
18
for performing series/parallel conversion to interface write and read data of the memory bank with outside; an input/output terminal
20
for outputting read data received through the upper and lower series/parallel shifter units
16
,
18
to outside and for outputting write data received from outside to the upper and lower series/parallel shifter units
16
,
18
; and a control unit
22
for controlling operations of the upper and lower series/parallel shifter units
16
,
18
.
The memory blocks
10
have 32 memory banks, including the upper memory block unit
12
and the lower memory block unit
14
comprising 16 banks respectively.
The upper series/parallel shifter unit
16
converts 128 bit parallel data RDA_top[127:0] read in the upper memory block unit
12
to 16 bit data EvenRDA_top[7:0], OddRDA_top[7:0] and outputs the result and the lower series/parallel shifter unit
18
converts 128 bit parallel data RDA_bot[127:0] read in the lower memory block unit
14
to 16 bit data Even RDA_bot [7:0], OddRDA_bot [7:0] and outputs the result.
The upper and lower series/parallel shifter units
16
,
18
generally perform two operations. One of them is series-parallel conversion for converting 8 bit series data input 8 times in write operation to 128 bit and the other is parallel-series conversion for converting 128 bit data read from memory block in read operation to 8 bit×8.
In a write operation, two upper and lower series/parallel shifter units
16
,
18
simultaneously transmit inputted write data to the upper memory block unit
12
and the lower memory block unit
14
respectively and only the data selected by write address are recorded in the memory block
10
. And, in read operation, two upper and lower series/parallel shifter units
16
,
18
receive read data through each memory block
10
and transmit them to output terminal.
FIG. 2
is a block diagram of conventional memory bank control circuit disposed in the upper memory block
12
(or in the lower memory block
14
) shown in FIG.
1
. As illustrated, the conventional memory bank control circuit comprises: 16 memory bank units
30
<
0
>~
30
<
15
> for storing data; 17 sense amp units
40
<
0
>~
40
<
16
> disposed on upper parts and lower parts of each memory bank for sensing data in write and read operations; 17 sense amp driver units
50
<
0
>~
50
<
16
> for respectively controlling operations of the sense amp units
40
<
0
>~
40
<
16
>; ≠main word line and sub word line driver units
60
<
0
>~
60
<
15
> for driving word lines and sub word lines of the memory bank units
30
<
0
>~
30
<
15
>; and 16 control units and address latch units
70
<
0
>~
70
<
15
> for receiving active signals, precharge signals and global address signals from outside and generating sense amp control signals corresponding to address signals to control sense amp driver unit, main word line and sub word line driver unit and bit lines in memory bank, main word line control signals, sub word line control signals and bit line equalizing signals.
One control unit and one address latch unit are disposed in every memory bank unit
30
<
0
>~
30
<
15
>. When the active signal and the precharge signal are generated as global signals, the control unit and the address latch unit
70
<
0
>~
70
<
15
> of each memory bank check whether or not the received global address signals are address signals of its memory bank and then if the bank addresses correspond to each other, the memory banks are controlled to operate in active mode or precharge mode. That is, the control unit corresponding to the bank address and the address latch unit operate main word line and sub word line driver units of the relevant memory bank and 2 sense amp driver units on the upper and the lower parts of the relevant memory bank. Here, the control unit and the address latch unit selected by the bank address maintain word lines in the memory bank although external global address signals are changed by latching addresses received in active mode.
When nth memory bank
30
<n> is selected by the global address signal, all of (n−
1
)th, nth and (n+
1
)th memory banks
30
<n−
1
>,
30
<n>,
30
<n+
1
> are precharged and then the nth memory bank
30
<n> is activated. For example, if memory bank
1
30
<
1
> is selected, then memory bank
0
30
<
0
>, memory bank
1
30
<
1
> and memory bank
2
30
<
2
> are all precharged and then memory bank
1
30
<
1
>is activated. And, when the memory bank
1
30
<
1
> is activated, the memory bank
0
30
<
0
> and the memory bank
2
30
<
2
> are not activated until the memory bank
1
30
<
1
> is precharged.
However, the conventional bank control unit of Rambus DRAM has several drawbacks. For example, there is a problem of increased layout area since each memory bank has control units and address latch units.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the problems of the conventional bank control unit of Rambus DRAM. One object of this invention is to provide a bank control circuit capable of reducing circuit area by disposing one control circuit and one address latch circuit in every two banks.
According to the present invention, the semiconductor memory device wherein a dependent bank operation is performed, comprises: a plurality of banks including memory cells; a plurality of address latch circuits, shared by two adjacent banks respectively, for receiving global address signals and latching local address signals of the selected bank; and a plurality of control circuits, shared by two adjacent banks respectively, for generating control signals and determining the specific bank that is to be activated.
As described above, according to the present invention, one control circuit and address latch circuit is shared by two banks, thereby reducing circuit area.
The above objects and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings.


REFERENCES:
patent: 5241510 (1993-08-01), Kobayashi et al.
patent: 5528552 (1996-06-01), Kamisaki
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5893158 (1999-04-01), Furuta
patent: 5959929 (1999-09-01), Cowles et al.
patent: 5970016 (1999-10-01), Ohsawa
patent: 5973991 (1999-10-01), Tsuchida et al.
patent: 6028812 (2000-02-01), Tanaka
patent: 6049502 (2000-04-01), Cowles et al.
patent: 6075747 (2000-06-01), Won
patent: 6078536 (2000-06-01), Moon et al.
patent: 6119181 (2000-09-01), Vorbach et al.
patent: 6125422 (2000-09-01), May
patent: 6141290 (2000-10-01), Cowles et al.
patent: 6141765 (2000-10-01), Sherman
patent: 6154826 (2000-11-01), Wulf et al.
patent: 6185150 (2001-02-01), Toda et al.
patent: 60186949 (1985-09-01), None
patent: 7221762 (1995-08-01), None
patent: 149598 (2000-05-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device for controlling memory banks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device for controlling memory banks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device for controlling memory banks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3058418