Semiconductor memory device for a rapid random access

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36523006, 3652385, G11C 800

Patent

active

060349115

ABSTRACT:
A random access memory device includes a plurality of memory blocks, a memory block selecting circuit and a column decoder. Each memory block comprise a memory cell array including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells, and a peripheral circuit including sense amplifiers which amplify data read out onto bit line pairs when a memory block select signal for a particular memory block is active to connect all memory cells contained in one row with associated bit line pairs. An access control circuit changes a block address and a column address while maintaining a row address unchanged, thus performing a rapid random access of memory cells contained in a common row over the memory blocks.

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