Semiconductor memory device equipped with column decoder outputt

Details Semiconductor memory device equipped with column decoder outputt Semiconductor memory device equipped with column decoder outputt

1997-08-18

2000-08-08

Zarabian, A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365207, 365190, G11C 800

Patent

active

061011479

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention is related to a Dynamic Random Access Memory (DRAM) and, more particularly, to reliable DRAM timing for connecting memory cell data on a bit line to a data bus.
2. Description of Related Art
In the field of semiconductor memory devices, various technological improvements have been promoted and proposed from the view point of a high speed operation and high integration.
An example was disclosed in Japanese Patent Publication: JP-A-3165398 published on Jul. 17, 1991, which aimed at a high speed memory device by improving a column decoder providing a memory cell array with a column selection signal. Another example was disclosed in the U.S. Pat. No. 4,344,005 issued on Aug. 10, 1982, which devised the method of controlling a column decoder.
However, it is an object of the present invention to provide a semiconductor memory device that can perform at higher speed and with more reliable operation by further improving various memory devices which have been proposed and improved.
It is another object of the present invention to provide a semiconductor memory device-which does not hinder a high integration and not complicate the manufacturing process, which memory device can be realized by a simple design.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram typically and partially illustrating a circuit of a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a configuration of the first type unit decoder applied to a column decoder of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of the second type unit decoder applied to a column decoder of the present invention.
FIG. 4 is a timing chart partially illustrating an outline of operation of the semiconductor memory device shown in FIG. 1.
FIG. 5 is a chart explaining a potential relation between a column selection signal and a bit line according to the present invention.
FIG. 6 is a chart explaining a potential relation of a bit line, a column line, and a data bus.
FIG. 7 is a chart explaining another potential relation of a bit line, a column line, and a data bus.
FIG. 8 is a chart explaining a setting range of a driving potential.
FIG. 9 is a circuit diagram partially illustrating an example in which a power supply switching circuit is applied to the semiconductor memory device according to the present invention.
FIG. 10 is a circuit diagram partially illustrating another embodiment of the present invention.
FIG. 11 is a circuit diagram partially illustrating still another embodiment of the present invention.


DESCRIPTION OF THE PREFERRED EMBODIMENT

Best mode for carrying out the present invention will be described hereinafter with reference to the accompanying drawings. The drawings used for this description typically illustrate major characteristic parts in order that the present invention will be easily understood. In this description, one embodiment is shown in which the present invention is applied to a DRAM.
FIG. 1 is a circuit diagram partially illustrating an outline of a semiconductor memory device according to the present invention.
A semiconductor memory device (DRAM) 100 comprises a plurality of memory celis MCi,j (i=1, 2, . . . n, j=1, 2, . . . m) to store data, bit line pairs BL1, /BL1.about.BLm, /BLm each connecting to each memory cells, word lines WL1.about.WLn for transferring row selection signals that select memory cells, sense amplifiers SA1.about.SAm for amplifying the potential on each bit line, transfer gate pairs TG1, /TG1,.about.TGm, /TGm for connecting the bit line pairs to data bus pair DB, /DB in response to column selection signals supplied to column lines CL1.about.CLm, a row decoder 101 for supplying the row selection signals based on a row address XADD provided from outside, a column decoder 103 for supplying the column selection signals based on a column address YADD provided from outside, and an input output circuit 105 connected to the d

REFERENCES:
patent: 4344005 (1982-08-01), Stewart
patent: 5305261 (1994-04-01), Furutami et al.
patent: 5327386 (1994-07-01), Fudeyasu

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