Semiconductor memory device employing sense amplifier control ci

Details Semiconductor memory device employing sense amplifier control ci Semiconductor memory device employing sense amplifier control ci

1994-07-25

1995-12-26

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365202, 365203, 365190, 365207, 365227, G11C 700

Patent

active

054793742

ABSTRACT:
A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.

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patent: 5327394 (1994-07-01), Green et al.
patent: 5343432 (1994-08-01), Matsuo et al.
Minato, Osamu, et al. "Session XV: Static RAMs THPM 15.5: A 20ns 64K CMOS SRAM" ISCC Digest of Technical Papers, pp. 222-223, Feb. 23, 1984.
Matsui Masataka, et al., "Two Power-Down Circuits on the 1Mb CMOS SRAM" Proc. Symp. VLSI Circ. (Tokyo), Aug. 1988, pp. 55-56.

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