Semiconductor memory device employing pipeline operation...

Details Semiconductor memory device employing pipeline operation... Semiconductor memory device employing pipeline operation...

2000-04-13

2002-02-26

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230010, C365S189070

Reexamination Certificate

active

06351433

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a synchronous semiconductor memory device employing a pipeline operation that consumes less power.
2. Description of the Background Art
A synchronous semiconductor memory device employing a pipeline operation is disclosed, for example, in U.S. Pat. No. 5,838,631, which prevents conflict of read data with write data at a data terminal to speed up the operation.
FIG. 7
is a block diagram illustrating a configuration of a conventional synchronous semiconductor memory device
5000
employing the pipeline operation, disclosed in the above-mentioned U.S. Pat. No. 5,838,631.
Referring to
FIG. 7
, semiconductor memory device
5000
includes: a terminal group
110
externally sending and receiving data, a clock signal and a control signal; a memory array circuit
120
for storing the externally sent and received data in a memory cell; a control circuit
130
for controlling reading/writing operations with memory array circuit
120
and data input/output at terminal group
110
according to the externally supplied control signal; and a write data retaining circuit
140
and a write address retaining circuit
150
for temporarily retaining, respectively, write data of which writing is designated and its corresponding address. Semiconductor memory device
5000
is able to temporarily retain two pieces of write data by write data retaining circuit
140
and write address retaining circuit
150
. Accordingly, in semiconductor memory device
5000
, sending and receiving of input/output data at a data terminal is performed
2
clock cycles later than the input of the corresponding address signal.
Data terminal group
110
receives a chip select signal CS# for driving a chip into a selected state, a clock enable signal CKE# for selecting an enabled/disabled state of the chip, a reference clock signal CLK, an address signal ADD consisting of address bits A
0
-An, and a write enable signal WE#. Data terminal group
110
includes a data terminal
19
performing data input/output.
An address register AReg.
0
operates as an address buffer for taking in an address signal in response to each activation edge of reference clock signal CLK, and outputs an input address AR
0
in each clock cycle.
Memory array circuit
120
, having therein a plurality of memory cells arranged in rows and columns as storage elements, responds to a control signal output from control circuit
130
for reading data out of or writing data into a memory cell selected by an address signal. Although not shown, memory array circuit
120
includes memory cells arranged in rows and columns, a decoder for selecting a memory cell corresponding to an address signal, an input/output circuit for writing and reading data to and from a memory cell, and others. These features are collectively shown as memory array circuit
120
in FIG.
7
. In other words, memory array circuit
120
responds to a control signal supplied from control circuit
130
to its signal terminals READ# and WRITE#, and performs a reading operation or a writing operation of data for the memory cell that corresponds to the address signal input to address terminal ADR. The write data for use in the writing operation are input from data terminal IN, and the read data being output from a memory cell by the reading operation are output from data terminal OUT.
When the chip is in an enabled state, i.e., when the clock enable signal is in an active state (at an L level), control circuit
130
responds to each activation edge of reference clock signal CLK and takes in the signal levels of control signals CS# and WE# at the relevant clock cycle, while retaining their signal levels of one clock cycle before.
In response to the combination of the signal levels, control circuit
130
generates control signals WB
1
, WB
2
, RB and the like, which are updated in response to each activation edge of reference clock signal CLK. Control signal WB
1
is activated when the chip is in a selected state and the writing operation is designated by write enable signal WE# in the relevant clock cycle. Control signal RB is activated when the chip is in a selected state and the reading operation is designated by write enable signal WE# in the relevant clock cycle. Control signal WB
2
is a signal which retains the signal level of control signal WB
1
one clock cycle before, and it designates which should be performed at data terminal
19
, data input or data output, at the next activation edge of reference clock signal CLK.
Write data retaining circuit
140
takes in and temporarily retains write data input to data terminal
19
by two register circuits DReg.
1
and DReg.
2
that are enabled in response to control signal WB
2
.
Write address retaining circuit
150
receives input address AR
0
from address register AReg.
0
, and retains storage addresses AR
1
and AR
2
that correspond to the write data stored in write data retaining circuit
140
by two register circuits Areg.
1
and Areg.
2
, that are enabled in response to the output of a logic gate
11
that outputs an OR logical operation result of control signal WB
1
and clock enable signal CKE#.
An address matching circuit
160
includes address comparison circuits
30
and
32
which perform matching of input address AR
0
with respective storage addresses AR
1
and AR
2
stored in address retaining circuit
150
. Address comparison circuit
30
activates an address match signal EQ
1
(to an H level) when input address AR
0
matches storage address AR
1
. Address comparison circuit
32
activates an address match signal EQ
2
(to an H level) when input address AR
0
matches storage address AR
2
. If at least one of the two signals is activated, it means that an address corresponding to the write data that have been input from the data terminal but not yet written into memory array circuit
120
is now a target for the reading operation. In this case, there is a need to set a data path which permits the stored write data to be directly read out from the data terminal, instead of read data being directly output from the memory array circuit.
FIG. 8
is a block diagram illustrating configurations of address comparison circuits
30
and
32
.
In
FIG. 8
, a configuration corresponding to each bit of address signal ADD is shown. Referring to
FIG. 8
, bits A
0
to An of address signal ADD are supplied to address input terminals
4
-
0
to
4
-
n,
respectively. Connected to each address input terminal are three address registers, which correspond to address registers AReg.
0
to AReg.
2
shown in FIG.
7
. For example, address registers AReg.
00
, AReg.
10
and AReg.
20
are provided for address signal bit A
0
input to address input terminal
4
-
0
. As seen in
FIG. 7
, address register AReg.
00
receives clock enable signal CKE# as its operation enable signal, and address registers AReg.
10
and AReg.
20
each receive the output of logic gate
11
as its operation enable signal. Each bit of the address signal is provided with a similar register circuit group. With such a configuration, signals AR
00
to AR
0
n
are obtained for respective bits corresponding to input address AR
0
as shown in
FIG. 7
, and signals AR
10
to AR
1
n
and AR
20
to AR
2
n
are also obtained for respective bits corresponding to storage addresses AR
1
and AR
2
.
Address comparison circuit
30
has address comparison units COMP
10
to COMP
1
n.
Address comparison unit COMP
10
includes: a logic gate
52
that receives AR
00
and AR
10
to output their NAND logical operation result; a logic gate
53
that receives inverted signals of AR
00
and AR
10
to output their AND logical operation result; an inverter
54
that inverts an output of logic gate
53
; and a logic gate
55
that receives inverted signals of respective outputs of logic gate
52
and inverter
54
to output their OR logical operation result. The output of logic gate
52
attains an L level when AR
00
and AR

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