Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-06-29
2001-07-31
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S201000
Reexamination Certificate
active
06269044
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device utilizing semiconductor memories and, more particularly, to the semiconductor memory device having a function for detecting the presence or absence of an abnormal current consumption resulting from defects or the like that are found in transistors forming a sense amplifier.
2. Description of the Prior Art
Conventionally, in a semiconductor memory device comprising a plurality of operating blocks, there are cases where the current consumption changes depending on activated operating blocks because of the uneven characteristics or imperfection of the transistors forming the sense amplifier.
FIG. 7
is a schematic diagram showing a configuration of a semiconductor memory device according to the prior art. In
FIG. 7
, a semiconductor memory device comprising four operating blocks is shown as an example, and in particular an activation circuit for each sense amplifier circuit of the semiconductor memory device is shown.
In
FIG. 7
, a semiconductor memory device
100
is provided with a sense amplifier circuit comprising a plurality of sense amplifiers, four operating blocks
101
to
104
comprising row decoders and memory cell blocks, an operating block selecting circuit
105
for selecting and activating operating blocks
101
to
104
based on a block selecting signal from the outside.
The operating block selecting circuit
105
takes a logical product between sense amplifier activation signals SP and SN inputted from the outside and block selecting signals BS
1
to BS
4
inputted from the outside, and generates internal sense amplifier activation signals ZSP
1
to ZSP
4
and SN
1
to SN
4
, respectively, for respective sense amplifier circuits in each operating block
101
to
104
to be outputted to the corresponding sense amplifier circuit, respectively. A character “Z” affixed to reference characters ZSP
1
to ZSP
4
each representing the internal sense amplifier activation signal indicates a negative logic, that is to say, Low active.
As for the block selecting signals BS
1
to BS
4
inputted from the outside, they are inputted so that at least one of the signals is activated and all of the selecting signals are not activated simultaneously. Therefore, only the sense amplifier circuit of at least one operating block among the operating blocks
101
to
104
is activated and all the sense amplifier circuits are not activated simultaneously. Here, it is assumed that a sense amplifier in the sense amplifier circuit of the operating block
104
among the operating blocks
101
to
104
is defective and an abnormal current flows only when the sense amplifier circuit of the operating block
104
is activated. The abnormal current is a current which is not supposed to flow between the power terminal Vdd and the ground, which has a larger OFF current, a leak current when the transistor is turned off, than normal and which can be detected only when an abnormal sense amplifier circuit is activated.
FIG. 8
is a schematic circuit diagram showing an example of the sense amplifier circuit of the operating block
104
.
FIG. 8
shows the case where a sense amplifier circuit
111
of the operating block
104
comprises (n+1) sense amplifiers SA
0
to SAn. In
FIG. 8
, in the case that for example N-channel metal oxide semiconductor field effect transistors (hereinafter referred to as NMOS transistors) Qa and Qb are defective and a leak current between the source and the drain when the NMOS transistors Qa and Qb are turned off is larger then normal, the above described abnormal current flows between the power terminal Vdd and the ground.
FIG. 9
is a diagram showing a waveform of each signal when the sense amplifier circuit
111
in
FIG. 8
is activated, which shows the case when NMOS transistors Qa and Qb are defective. Here, BL
0
and ZBL
0
show bit lines connected to the sense amplifier SA
0
, and “Z” of the bit line ZBL
0
indicates that it is Low active and hereinafter reference characters with “Z” attached in the front represents that they are Low active.
As shown in
FIG. 9
, only when the sense amplifier SA
0
having defective NMOS transistors Qa and Qb is activated, that is, only when the sense amplifier circuit
111
of the operating block
104
is activated, the leak current of the semiconductor memory device
100
shows an abnormal value and in the case that other normal operating blocks
101
to
103
are activated, the leak current shows a normal value as exhibited with a broken line. Therefore, in the case that a test is carried out to find whether or not the operating current of the semiconductor memory device
100
satisfies a predetermined standard value, it is necessary to perform a current measurement while switching the operating blocks
101
to
104
because the current consumption differs depending on the operating block, which has a problem that the test time takes too long.
On the other hand, in the case that a defective sense amplifier in the sense amplifier circuit is activated, there is a possibility that the operating current value of the sense amplifier circuit part may change according to a logical condition of the bit line due to a position of the defective transistor of the sense amplifier. For example, in
FIG. 8
, it is assumed that the NMOS transistor Qa is defective where the OFF current is larger than normal. In this case, when the bit line ZBL
0
is at High level and the bit line BL
0
is at Low level, an abnormal current flows through the NMOS transistor Qa because it carries out a current pass. However, when the bit line ZBL
0
is at Low level and the bit line BL
0
is at High level, an abnormal current does not flow because the NMOS transistor Qa is irrelevant of a current pass.
To detect such a defect of the sense amplifier without fail, the operating current may be measured while changing the combinations of the logical conditions of the bit lined BL
0
and ZBL
0
, but at that time they need to have ordinal writing operations.
FIG. 10
is a diagram showing a waveform of each part in
FIG. 8
in the ordinal writing operation. Here, WBE in
FIG. 10
shows an activation signal inputted from the outside to a writing buffer
112
in FIG.
8
.
As shown in
FIG. 10
, in the ordinal writing operation, the writing operation can be carried to the sense amplifiers one at one time and, therefore, there is a problem that it takes too long to have the writing operations for all sense amplifiers. And because each sense amplifier has a cross couple of two inverters, it is still difficult to perform the writing operations for all sense amplifiers in the sense amplifier circuit part simultaneously due to the lack of the ability of the writing buffer
112
even though column selecting lines CSLO to CSLn are activated simultaneously at the time of writing operations.
In the Japanese Patent Laid-Open Publication No. 5-6699 published on Jan. 14, 1993, it is disclosed that a plurality of sense amplifiers are activated simultaneously in order to shorten the test time of memory elements, and in the Japanese Patent Laid-Open Publication No. 9-91993 published on Apr. 4, 1997, it is disclosed to activate a plurality of word lines simultaneously in order to shorten the test time of writing to memory elements.
SUMMARY OF THE INVENTION
The present invention has been developed to substantially eliminate the above described problems, and has for its object to provide a semiconductor memory device which can detect, in a short time without fail, an abnormal operating current which occurs due to the defect of a transistor forming a sense amplifier circuit provided for each operating block.
A semiconductor memory device according to the present invention is provided with memory cell blocks formed with a memory cell alley, a sense amplifier provided corresponding to each bit line of the memory cell block and a plurality of operating blocks each of which is formed from a variety of decoders or the like. The semiconductor memory device includes an operating blo
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Tran M.
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