Semiconductor memory device, electronic card and electronic...

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S051000, C365S205000

Reexamination Certificate

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11172252

ABSTRACT:
A semiconductor memory device comprises a cell array including bit lines arranged at a uniform pitch; and a plurality of bit line selection transistors connected to respective bit line ends for selectively connecting the bit line to a sense amp. The bit line selection transistors are translationally arrayed in a direction perpendicular to the bit line at an average array pitch greater than eight times the pitch of the bit lines.

REFERENCES:
patent: 5859805 (1999-01-01), Takashima et al.
patent: 5917744 (1999-06-01), Kirihata et al.
patent: 6067249 (2000-05-01), Lee et al.
patent: 6927990 (2005-08-01), Mukai

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