Semiconductor memory device divided into blocks and operable to

Details Semiconductor memory device divided into blocks and operable to Semiconductor memory device divided into blocks and operable to

1992-09-29

1994-02-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518901, 36518904, G11C 800, G11C 700

Patent

active

052894312

ABSTRACT:
In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

REFERENCES:
patent: 4725945 (1988-02-01), Krowstadt et al.
patent: 4755971 (1988-07-01), Jasmer et al.
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 5060145 (1991-10-01), Scheuneman et al.
"A 1.5V Circuit Technology for 64Mb DRAMs", Y. Nakagome et al., IEEE 1990 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 17-18.
"A 40ns 64Mb DRAM with Current-Sensing Data-Bus Amplifier", M. Taguchi et al., 1991 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 112-113.

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