Semiconductor memory device delaying ATD pulse signal to generat

Details Semiconductor memory device delaying ATD pulse signal to generat Semiconductor memory device delaying ATD pulse signal to generat

1999-03-12

1999-10-26

Nelms, David

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365194, 3652335, G11C 800

Patent

active

059739878

ABSTRACT:
A word line activation signal generated by a timing generator is surely at L level in a prescribed period regardless of the power supply voltage. A row address signal delayed by a delay circuit in a row address buffer changes in a period in which the word line activation signal is at L level. Accordingly, even if skew occurs, a non-selected word line is never activated. Consequently, it is possible to prevent delay of access to a memory cell and erroneous writing to a memory cell.

REFERENCES:
patent: 5323360 (1994-06-01), Pelley et al.
patent: 5414672 (1995-05-01), Ozeki et al.
patent: 5457661 (1995-10-01), Tomita et al.
patent: 5608688 (1997-03-01), Park
patent: 5636177 (1997-06-01), Fu
patent: 5719812 (1998-02-01), Seki et al.

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