Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-01-19
2002-09-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189040, C365S235000
Reexamination Certificate
active
06449209
ABSTRACT:
BACKGROUND
A conventional semiconductor memory device typically includes multiple memory banks where each memory bank has the same size (i.e., the same number of memory cells) and the same storage capacity. In particular, a standard memory architecture now commonly employed for dynamic random access memory (DRAM) includes four memory banks of equal size. For example, a typical 64-Mbit DRAM has four banks, and each bank has a 16-Mbit storage capacity. An advantage of having multiple banks is that the banks can operate independently so that multiple pages, e.g., one in each bank, can remain simultaneously active. Accordingly, the probability of a page hit is higher, and the multi-bank memory typically provides an average data rate or bandwidth that is higher than the average data rate or bandwidth of a single-bank memory of the same size. A disadvantage of having multiple banks is the additional overhead circuits required when implementing the same functions in parallel in multiple banks. With these tradeoffs, four banks are suitable for a typical memory architecture.
As memory capacities have increased, the sizes of the banks have proportionally increased. For example, with the standard four-bank architecture, each bank in a 256-Mbit DRAM has a 64-Mbit capacity, and each bank in a 1-Gbit or larger DRAM must contain 256 Mbits or more of storage.
Large banks in a semiconductor memory device can reduce memory performance particularly when multiple master devices access the semiconductor memory device. For example, for full utilization of memory capacity, a master device requiring a relatively small buffer (i.e., smaller than a bank) often shares a bank with another master device. However, independent master devices commonly require different data, and the probability of an access causing a page miss, which degrades performance, is high when two master devices share the same bank. For example, a page miss results if a second master accesses a second word line of a first memory bank after a first master accesses a first word line of the first memory bank.
FIG. 4
shows a conventional read operation when a first row is currently selected in a bank but the read operation accesses a second row in the bank. With this page miss in the bank, an initial command at a time TO causes pre-charging of the word lines of the target bank. The precharging requires a precharge time tRP. The following command at time T
2
causes a delay time tRCD for activating or enabling the second word line. At time T
4
, after enabling the second word line, a time CL (CAS Latency) is required for receiving a column address and outputting the data at time T
6
. In contrast, consecutive accesses of memory cells on the same row line in a bank require only the CAS latency time CL for output of data. Accordingly, having a series of interleaved accesses of different row lines causes significant delays and significantly degrades the system's performance.
To improve system performance, a memory device is needed that reduces the probability of page misses and increases the probability of page hits even when used with multiple masters. One way to reduce page misses and increase page hits is to include more (and therefore smaller) banks in a memory device so that no two masters share the same bank. However, increasing the number of banks increases the required amount of overhead circuitry, which increases the area and cost of an integrated memory circuit. Accordingly, memory technology needs memory architectures and methods that reduce page misses in a system with multiple master devices without significantly increasing the overhead circuitry or cost of the integrated memory device.
SUMMARY
In accordance with an aspect of the invention, a semiconductor device has multiple memory banks having different sizes for use with multiple master devices. With this architecture, each master device can be assigned a bank or banks having storage capacity matching the storage requirements of the master device. Accordingly, master devices that might interleave accesses to different data are more easily prevented from interleaved accesses to different row lines in the same bank. This reduces the number of page misses and improves average bandwidth or data rate of the memory.
One embodiment of the invention is an integrated circuit memory such as an SDRAM that includes a first memory bank containing a first number of memory cells and a second memory bank containing a second number of memory cells, wherein the second number differs from the first number. The first bank has a first row decoder that can keep a row line in the first bank activated for access to a memory cell in the first bank while a second row decoder in the second bank keeps another row line in the second bank activated for access. Generally, since the banks have different sizes, the number of bits in an internal row address provided to the first row decoder often differs from the number of bits in an internal row address provided to a second row decoder. Third and subsequent banks in the memory can have sizes that are the same as or different from the sizes of the first and second banks.
Another embodiment of the invention is a system including a plurality of master devices and an integrated circuit memory. The master devices include a first master device requiring a first buffer having a first size and a second master device requiring a second buffer having a second size that differs from the first size. The integrated circuit memory, which provides storage that implements the first and second buffers, includes a plurality of banks including a first bank containing a first number of memory cells and a second bank containing a second number of memory cells, the second number differing from the first number. To reduce page misses during memory accesses, the first master device is configured to access the first bank for access to the first buffer, and the second master device is configured to access the second bank for access to the second buffer. Typically, a memory control circuit controls access to the integrated circuit memory from the master devices.
Yet another embodiment of the invention is a method for operating a system including multiple master devices where each master device requires a buffer. This method includes: employing an integrated circuit memory comprising a plurality of banks wherein at least two of the banks differ from each other in size; assigning the plurality of banks to the plurality of master devices so that each master device has a corresponding bank and the corresponding bank has a size sufficient for the buffer that the master device requires; and directing access operations of each master device to the corresponding bank. The method can interleave a first master device's access of a first row address and a second master device's accesses of a second row address such that the first and second master devices access different banks. Accordingly, the interleaved access do not cause repeated page misses that would requires pre-charging or re-activation of the first row line after each access by the second master device.
REFERENCES:
patent: 5412613 (1995-05-01), Galbi et al.
patent: 5638321 (1997-06-01), Lee et al.
patent: 6104641 (2000-08-01), Itou
patent: 6111787 (2000-08-01), Akaogi et al.
patent: 6130836 (2000-10-01), Matsubara et al.
Nguyen Van Thu
Skjerven Morrill LLP
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