Static information storage and retrieval – Format or disposition of elements
Patent
1992-01-16
1993-02-02
Dixon, Joseph L.
Static information storage and retrieval
Format or disposition of elements
365 63, 257920, G11C 506
Patent
active
051843218
ABSTRACT:
A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.
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Dosaka Katsumi
Inoue Yoshinori
Komatsu Takahiro
Konishi Yasuhiro
Kumanoya Masaki
Dixon Joseph L.
Lane Jack A.
Mitsubishi Denki & Kabushiki Kaisha
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