Semiconductor memory device comprising a p-n junction in a polyc

Details Semiconductor memory device comprising a p-n junction in a polyc Semiconductor memory device comprising a p-n junction in a polyc

1978-01-10

1980-01-15

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 23, 357 41, 357 59, 365186, G11C 1140, H01L 2704

Patent

active

041840852

ABSTRACT:
A semiconductor memory device of a surface-charge type comprises a p-type silicon substrate having a silicon dioxide film thereon and memory cells partly in the substrate and partly thereon in rows and columns. Each cell comprises an n.sup.+ -type region beneath the oxide film, a polysilicon layer on the oxide film, and an insulator film integral on the polysilicon layer with the oxide films at positions where the polysilicon layer is not present. The polysilicon layer comprises a p-type portion serving as a storage capacitor electrode and an n-type portion forming a p-n junction with the p-type portion. The n-type portion is common to cells of each column to serve as a transfer gate electrode and a word line. A metal film formed on the insulator film is connected to the n.sup.+ -type region of cells of each row to serve as a bit line. That region of the substrate which is opposite to the capacitor electrode is doped with a donor to insure storage of information-representative charges even with the capacitor electrode grounded. To reduce the resistance of the capacitor electrode, an intermediate metal film may be formed on the capacitor electrode except at its portion adjacent to the p-n junction.

REFERENCES:
patent: 3855610 (1974-12-01), Masuda et al.
patent: 3858232 (1974-12-01), Boyle et al.
patent: 3865654 (1975-02-01), Chang et al.
patent: 3943545 (1976-03-01), Kim
patent: 4060738 (1977-11-01), Tasch, Jr. et al.
Ho et al., IBM Tech. Discl. Bulletin, vol. 15, No. 2, Jul. 1972, pp. 412-413.

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