Semiconductor memory device comprised of a double data...

Details Semiconductor memory device comprised of a double data... Semiconductor memory device comprised of a double data...

1999-10-27

2001-01-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230040, C365S230080

Reexamination Certificate

active

06178139

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device comprised of a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory).
2. Description of the Related Art
As a CPU (central processing unit) to control operations of a computer is becoming increasingly faster, a SDRAM (synchronous dynamic random access memory) adapted to operate in synchronization with a clock is used widely. In order to achieve further faster CPUs, 2 bit prefetch-type SDRAMs have come into use which allow simultaneous writing and reading of 2 bits of data.
FIG. 50
is a block diagram showing an example of configurations of a conventional semiconductor memory device comprised of 2 bit prefetch-type SDRAMs.
FIG. 51
is a timing chart explaining operations of the conventional semiconductor memory device at the time of writing of data.
FIG. 52
is a timing chart showing operations of the conventional semiconductor memory device at the time of reading of data.
As depicted in
FIG. 50
, the conventional semiconductor memory device is provided approximately with memory cell arrays
1
and
2
, word drivers
3
and
4
, DIN/DOUT (Data In/Data Out) circuits
5
and
6
, write amplifiers
7
and
8
, sense amplifiers
9
,
10
,
11
and
12
, column decoders
13
and
14
, a command decoder
15
, a burst counter
16
and a column control circuit
17
.
The memory cell arrays
1
and
2
contain two or more memory cells arranged in a matrix form. Word drivers
3
and
4
are used to drive each word line for the memory arrays
1
and
2
. The DIN/DOUT circuits
5
and
6
are adapted to output, in response to write operation controlling signals W
0
and W
1
, data outputs RWBS and RWBS* (the symbol * representing an inversion signal) composed of complementary signals to respond to data inputs DQ fed through even-numbered and odd-numbered data buses respectively. They are also adapted to output data outputs DQ to even-numbered and odd-numbered data buses in response to read operation controlling signals R
0
and R
1
when receiving data inputs RWBS and RWBS* composed of complementary signals. The write amplifiers
7
and
8
are used to amplify data outputs RWBS and RWBS* and to output writing inputs IO and IO* composed of complementary signals. The sense amplifiers
9
and
10
are used to amplify a writing voltage to be applied to memory cells connected to each bit line constituting the memory cell array
1
as well as a reading voltage to be supplied from the memory cell. The sense amplifiers
11
and
12
are used to amplify the writing voltage to be applied to memory cells connected to each bit line constituting the memory cell array
1
as well as the reading voltage to be supplied from the memory cell.
The column decoders
13
and
14
are adapted to select each bit line for each of memory cell arrays
1
and
2
in response to address inputs and to drive a column selecting line CSL selected. The command decoder
15
is used to generate a read/write command RWCMD and address controlling signals YAL and NYAL, each being an internal command signal, in response to external command signals CSB (command select bar), RASB (RAS bar), CASB (CAS bar), WEB (write enable bar) and a clock signal CLK. The burst counter
16
, after generating address outputs in response to address inputs composed of, for example, 8 bits with a timing defined by the address controlling signal YAL, perform repeated processing of sequentially generating an address output with 2 added at each time of the occurrence of an address controlling signal NYAL, every two clocks, for a period corresponding to a specified burst length (e.g., word length). The column control circuit
17
serves to output write operation controlling signals W
0
and W
1
or read operation controlling signals R
0
and R
1
to be fed to the DIN/DOUT circuits
5
and
6
in response to a read/write command RWCMD from the command decoder
15
and an address output from the burst counter
16
.
Next, operations of the conventional semiconductor memory device at the time of writing by referring to
FIGS. 50 and 51
. Let it be assumed that a command input CMD is a write command W CMD and that D
0
, D
1
, D
2
and D
3
are inputted as data input DQ in response to a clock signal CLK. At this point, in response to the read/write command RWCMD from the command decoder
15
, write operation controlling signals W
0
and W
1
are outputted from the column control circuit
17
.
On the other hand, when address inputs IA
0
to IAj are generated in response to designated address signals A
0
to Aj from the CPU (not shown), address signals YP
0
to YPj are outputted from the burst counter
16
in response to an address controlling signal from the command decoder, and then 2 clocks later, in response to the address controlling signal NYAL, an address signal obtained by adding 2 (in the case of 2 bit prefetch type) to addresses YP
0
to YOj is outputted from the burst counter
16
.
At this point, even-numbered data D
0
and odd-numbered data D
1
are outputted from the DIN/DOUT circuits
5
and
6
as data outputs RWBS and RWBS* in response to write operation controlling signals W
0
and W
1
, and data D
0
and D
1
are outputted as writing data IO and IO* from the write circuits
7
and
8
and are written into memory cells of column selecting lines CSL
0
and
1
defined by addresses YP
0
to YOj. Moreover, in response to subsequent write operation controlling signals W
0
and W
1
, data D
2
and D
3
are outputted as data outputs RWBS and RWBS*, and data D
2
and D
3
are outputted as writing data IO and IO* and are written into memory cells of column selecting lines CSL
2
and
3
defined by addresses YP
0
to YPj (+2) as well.
Next, operations of the conventional semiconductor memory device at the time of reading of data by referring to
FIGS. 50 and 52
are hereafter described.
When the command input CMD is a read command R CMD and address inputs IA
0
to IAj are generated in response to designated address signals A
0
to Aj from the CPU, address signals YP
0
to YPj are outputted from the burst counter
16
in response to an address controlling signal YAL from the command decoder
15
, and then an address obtained by adding
2
to address signals YP
0
to YPj is outputted from the burst counter
16
in response to the address controlling signal NYAL. This causes Q
0
and Q
1
as read data IO and IO* read out from column selecting lines CSLO and
1
defined by address signals YPO to YPj to be outputted and Q
2
and Q
3
to be outputted from column selecting lines CSL
2
and
3
defined by address signals YP
0
to YPj (+2).
On the other hand, the column control circuit
17
is used to output, every 2 clocks, read operation controlling signals R
0
and R
1
in response to the read/write command RWCMD, causing data Q
0
, Q
1
, Q
2
and Q
3
as read data RWBS and RWBS* to be outputted and, as a result, the DIN/DOUT circuits
5
and
6
output, 5 clocks later (CLT=5) which is a specified output timing, data Q
0
, Q
1
, Q
2
and Q
3
, every one clock, as read data DQ.
As described above, in the conventional semiconductor memory device composed of the 2 bit prefetch-type SDRAM, in order to have it operate in synchronization with a clock signal and to build up its operational speed, it is necessary to make the transmission of a clock signal faster. However, in a computer using the SDRAM, when the transmission of the clock signal is made faster, a problem of timing skew arises between the clock signal and data input signal, causing a limit to speeding-up of clock signals.
To solve this problem, the DDR-SDRAM is proposed in which capturing of a data input signal is carried out by a data strobe signal and a clock cycle is doubled compared with the data input cycle. The standardization of the DDR-SDRAM is in progress by JEDEC (Joint Electronic Device Engineering Council). The data strobe signal and data input signal are generated by the CPU at the sam

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