Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-02-07
2001-02-13
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060
Reexamination Certificate
active
06188631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a column select circuit for minimizing load to data input/output lines of a semiconductor device, a semiconductor memory device having the same, and a method of arranging the column select circuits in the semiconductor memory device.
2. Description of the Related Art
In general, approaches to improving performance of computer systems include improving the operational speed of the central processing unit (CPU) as well as the performance of memory devices that store data or programs required by the CPU. To improve the performance of the memory device, the bandwidth per unit time should be increased. The bit line data of a memory cell is selectively transferred to the data input/output lines through data input/output circuits, depending on the number of data input/output lines. Generally, the amount of data read from or written to the memory in a given time period, i.e., the bandwidth, directly depends on the number of data input/output lines.
The memory cell data loaded onto the data input/output lines of a semiconductor memory device determines the operational speed of the device. The operational speed of the semiconductor memory device is determined by the time between sensing the data stored in the memory cell to be read and outputting the data to the data input/output lines, or the duration required to transmit data to be written from the data input/output lines to the memory cell. Thus, the load applied to the data input/output lines should be reduced in order to prevent the operational speed of the semiconductor memory device from being reduced. The data input/output lines are connected to column select circuits, and thus a column select circuit should be able to minimize the load to the data input/output lines.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a column select circuit for minimizing the load applied to data input/output lines.
It is another object of the present invention to provide a semiconductor memory device having such a column select circuit.
It is still another object of the present invention to provide an efficient method of arranging the column select circuits in the semiconductor memory device.
To achieve the first object of the present invention, there is provided a semiconductor memory device having column select circuits, each column select circuit selecting one of at least two banks in a memory block and selecting a predetermined bit line among a plurality of bit lines in a selected bank to transfer data of the selected bit line to a data input/output line. The column select circuit includes a plurality of first select portions for connecting the bit lines of the selected bank to a corresponding first data lines in response to a bank select signal to select a predetermined bank. The column select circuit also includes a plurality of second select portions for connecting the first data lines to a second data line in response to a column select signal which represents the address of each bit line. The column select circuit also includes a third select portion for connecting the second data line to the data input/output lines in response to the bank select signal. The second data line shared by the second and third select portions is connected to at least one of the first data lines which is responsive to the column select signal.
To achieve the second object of the present invention, there is provided a semiconductor memory device for selecting a bank among a plurality of banks sharing data input/output lines. The banks are arranged in rows and columns. The device selects a predetermined bit line among a plurality of bit lines in the selected bank to transfer the data of the selected bit line to the data input/output lines. The semiconductor memory device includes column select circuits arranged between the banks. Each column select circuit is shared by the neighboring banks for transferring data of the selected bit line to the data input/output lines. Each column select circuit includes a plurality of first select portions for connecting the bit lines of the selected bank to the corresponding first data lines in response to a bank select signal to select a predetermined bank. Each column select circuit also includes a plurality of select portions for connecting the first data lines to a second data line in response to each column select signal which represents the address of each bit line. Each column select circuit also includes a third select portion for connecting the second data line to the data input/output lines in response to the bank select signal.
To achieve the third object of the present invention, there is provided an arrangement method for a semiconductor memory device for selecting a bank among at least two banks which share data input/output lines, the banks being arranged in units of memory blocks, and selecting a predetermined bit line among a plurality of bit lines in the selected bank, to transfer the data of the selected bit line to the data input/output lines. The semiconductor memory device includes a bit line sense amplifier for sensing the data of the bit lines and a column select circuit. The column select circuit (i) connects the bit lines of the selected bank to the corresponding first data lines through first select portions in response to a bank select signal to select a predetermined bank, (ii) connects the first data lines to a second data line through second select portions in response to each column select signal which represents the address of each bit line, and (iii) connects the second data line to the data input/output lines in response to the bank select signals. A sense amplifier power driver supplies power voltage to the bit line sense amplifier, and a data line equalizer equalizes the second data line. The sense amplifier power driver and the data line equalizer are arranged in the bit line sense amplifier region between the banks.
According to the present invention, even though the data input/output lines are shared by a number of banks, the junction load to the data input/output lines can be minimized. This is because the signal lines for column select signals, which are connected to second select portions of the column select circuit, are arranged in a direction parallel to the bit lines. Also, the data line equalizers and the sense amplifier power drivers are arranged in the bit line sense amplifier regions of the column select circuit, so that the chip size does not increase.
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Jeong Woo-pyo
Lee Jung-bae
Nguyen Tan T.
Samsung Electronics Co,. Ltd
Samuels , Gauthier & Stevens, LLP
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