Semiconductor memory device capable of switching reference...

Details Semiconductor memory device capable of switching reference... Semiconductor memory device capable of switching reference...

2001-08-08

2002-09-10

Mai, Son (Department: 2818)

Static information storage and retrieval

Powering

C365S189090, C365S201000

Reexamination Certificate

active

06449208

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having therein a voltage generating circuit for generating an intermediate voltage by switching a power source voltage when a mode is switched.
2. Description of the Background Art
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a plurality of internal source voltages are generated from an external source voltage extVdd supplied from the outside and are used. For example, a voltage Vddp to be supplied to peripheral circuits including a row decoder and a column decoder, an array operation voltage Vdds to be supplied to a memory array including a plurality of memory cells arranged in a matrix, a boosted voltage Vpp to be supplied to a wordline WL, and the like are generated from the external source voltage extVdd.
In a general DRAM, a precharge voltage Vbl for precharging a bit line for reading out data from a memory cell is generated so as to be the half of the array operation voltage Vdds by referring to the array operation voltage Vdds. A cell plate voltage Vcp to be supplied to one of electrodes (cell plate electrode) of a capacitor as a component of a memory cell is also generated by referring to the array operation voltage Vdds so as to be the half of the array operation voltage Vdds.
FIG. 9
shows a conventional typical half Vdds generating circuit. Referring to
FIG. 9
, a half Vdds generating circuit
40
D has a reference voltage generating circuit
42
and a driver circuit
44
. The reference voltage generating circuit
42
has resistors
421
and
424
, an N-channel MOS transistor
422
, and a P-channel MOS transistor
423
. The resistor
421
is connected between a power supply node
425
and a node
427
. The N-channel MOS transistor
422
and the P-channel MOS transistor
423
are diode-connected in series between the node
427
and a node
428
. The drain terminal of the N-channel MOS transistor
422
is connected to the node
427
and the drain terminal of the P-channel MOS transistor
423
is connected to the node
428
.
The resistor
424
is connected between the node
428
and a ground node
426
. The resistor
421
has a resistance value R
1
and a resistor
424
has a resistance value R
2
.
The driver circuit
44
is constructed by an N-channel MOS transistor
441
and a P-channel MOS transistor
442
. The N-channel MOS transistor
441
is connected between a power source node
443
and an output node
445
, and the P-channel MOS transistor
442
is connected between the output node
445
and a ground node
444
. The N-channel MOS transistor
441
receives a voltage on the node
427
in the reference voltage generating circuit
42
by its gate terminal. The P-channel MOS transistor
442
receives a voltage on the node
428
in the reference voltage generating circuit
42
by its gate terminal.
In the reference voltage generating circuit
42
, the array operation voltage Vdds is supplied from the power supply node
425
and is divided to a voltage determined by a resistance value R
1
of the resistor
421
and a voltage determined by a resistance value R
2
of the resistor
424
. The reference voltage generating circuit
42
outputs a voltage Vnd from the node
427
, and outputs a voltage Vpd from the node
428
. In this case, the voltages Vnd and Vpd are expressed by the following equations.
Vnd=Vn+Vthn
1
, Vpd=Vn−|Vthp
1|  (1)
where, Vn denotes a voltage on a node
429
, Vthn
1
denotes a threshold voltage of the N-channel MOS transistor
422
, and Vthp
1
denotes a threshold voltage of the P-channel MOS transistor
423
.
In the reference voltage generating circuit
42
, when the size of the N-channel MOS transistor
422
and that of the P-channel MOS transistor
423
are set to be large with respect to a through current from the power supply node
425
to the ground node
426
, a voltage Vn is expressed as the following equation.
Vn=|Vthp
1|+(
Vdds−Vthn
1
−|Vthp
1|)
×R
2/(
R
1
+R
2)  (2)
The voltage Vnd on the node
427
and the voltage Vpd on the node
428
are supplied to the gate terminals of the N-channel MOS transistor
441
and the P-channel MOS transistor
442
in the driver circuit
44
, respectively. In the case where a threshold voltage of the N-channel MOS transistor
441
and that of the P-channel MOS transistor
442
are set as Vthn
2
and Vthp
2
, respectively, when Vbl−Vpd>|Vthp
2
|, the P-channel MOS transistor
442
is turned on, a current flows from the output node
445
to the ground node
444
, and the precharge voltage Vbl decreases. When Vnd−Vbl>Vthn
2
, the N-channel MOS transistor
441
is turned on, a current flows from the power source node
443
to the output node
445
, and the precharge voltage Vbl increases. The voltage level of the precharge voltage Vbl is therefore controlled by the voltages Vnd and Vpd supplied from the reference voltage generating circuit
42
.
When Vthn
1
=Vthn
2
and Vthp
1
=Vthp
2
are satisfied, Vbl is equal to Vn from the equations (1) and (2), and the voltage level of the precharge voltage Vbl desired to be generated is determined by the resistance values R
1
and R
2
. Particularly, when R
1
=R
2
and Vthn
1
=Vthp
1
are satisfied at the same time, Vbl=Vdds/2, that is, the precharge voltage Vbl is equal to just the half of the array operation voltage Vdds.
By determining as described above the resistance values R
1
and R
2
of the resistors
421
and
424
of the reference voltage generating circuit
42
, the threshold voltages Vthn
1
and Vthp
1
of the N-channel MOS transistor
422
and the P-channel MOS transistor
423
, and the threshold voltages Vthn
2
and Vthp
2
of the N-channel MOS transistor
441
and the P-channel MOS transistor
442
of the driver circuit
44
, the half Vdds generating circuit
40
D generates the precharge voltage Vbl and the cell plate voltage Vcp each of which is the half of the array operation voltage Vdds.
In a normal mode of the DRAM, each of the precharge voltage Vbl and the cell plate voltage Vcp is controlled to be the half of the array operation voltage Vdds. In the case where the array operation voltage fluctuates, the precharge voltage Vbl and the cell plate voltage Vcp accordingly fluctuate so as to follow the fluctuation in the array operation voltage Vdds.
In a test mode, however, when the precharge voltage Vbl and the cell plate voltage Vcp fluctuate with the array operation voltage Vdds, a problem such that an accurate test of a memory cell cannot be conducted occurs.
For example, in some tests, the array operation voltage Vdds is increased only by &Dgr;Vdds to carry out a margin test of memory cells. Referring to
FIG. 10
, the array operation voltage Vdds is increased only by &Dgr;Vdds at time T
0
and is reset to a normal value at time T
1
. If the period from T
0
to T
1
is sufficiently long, the precharge voltage Vbl increases by &Dgr;Vdds/2.
Generally, a parasitic capacity of the precharge voltage Vbl is much larger than that of the array operation voltage Vdds. Consequently, even when the array operation voltage Vdds is reset to the normal value by time T
2
at which an operation test of a memory cell is to be conducted, the precharge voltage Vbl is not yet reset to the normal value. The voltage of a pair of bit lines BL and /BL of a memory cell from which data is read is therefore higher than the precharge voltage Vbl. This influences a sense operation performed at the time of reading data from the memory cell. When it is assumed that H-level data is read from a memory cell to the bit line BL, a voltage difference between the bit lines, BL and /BL, becomes smaller than that in the normal mode. It makes difficult for a sense amplifier to amplify the voltage difference to the full level, Vdds and ground.
This problem occurs also in the case where the array operation voltage Vdds is made lower than a normal value fo

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of switching reference... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of switching reference..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of switching reference... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2859541